Template Revision 2.12
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Important General Note:
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Note for Download Link of the Scroll ignore macro:
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Table of Contents |
The Trenz Electronic TEI0023 is a commercial-grade, low cost and small size module integrated with Intel® MAX 10. Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.
Actualize Link
Refer to https://wiki.trenz-electronic.de/display/PD/TEI0023+Resources for the current online version of this manual and other available documentation.
Notes :
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Note: Key Features' must be split into 6 main groups for modules and mainboards:
Key Features' must be split into 6 main groups for carrier:
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Intel® MAX 10 Commercial [10M08SAU169C8G]
Package: UBGA-169
Speed Grade: C8 (Slowest)
Temperature: 0°C to 85°C
Package compatible device 10M02...10M16 as assembly variant on request possible
SDRAM Memory up to 64Mb, 166MHz
Dual High Speed USB to Multipurpose UART/FIFO IC
64 Mb Quad SPI Flash
4Kb EEPROM Memory
8x User LED
Micro USB2 Receptacle 90
18 Bit 2 MSPS Analog to Digital Converter
2x SMA Female Connector
I/O interface: 23x GPIO
Power Supply: 5V
Dimension: 86.5mm x 25mm
add drawIO object here.
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Notes :
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SMA Connector, J5...6
Amplifier, U12
Series Voltage Reference, U8
Analog to Digital Converter, U6
Voltage Regulator, U4 - U10 - U13 - U16
Switching Voltage Regulator, U11
SDRAM Memory, U2
SPI Flash Memory, U5
Oscillator, U7 - U19
FTDI USB2 to JTAG/UART Adapter, U3
User LEDs, D2...9
FTDI Configuration EEPROM, U9
Configuration/Status LED (Red) , D10
Power-On LED (Green), D1
Push Button, S1...2
Micro USB Connector, J9
1x14 Pin Header, J2 (Not assembled)
1x6 Pin Header, J4 (Not assembled)
1x4 Pin Header, J3 (Not assembled)
1x14 Pin Header, J1 (Not assembled)
Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.
To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.
Reset process must be done by pressing push button S1.
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Notes :
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example:
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example:
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Notes :
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.
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There is a programmable clock generator on-board (U??) provided in order to generate variable clocks for the module. Programming can be done using I2C via PIN header J??. The I2C Address is 0x??.
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
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Power supply with minimum current capability of xx A for system startup is recommended.
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* TBD - To Be Determined
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? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)
Operating Temperature: -??°C ~ ??°C
Current Rating: ??A per ContactNumber of Positions: ??
Number of Rows: ??
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Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
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Module size: ?? mm × ?? mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ? mm.
PCB thickness: ?? mm.
In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:
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Set correct link to the shop page overview table of the product on English and German. Example for TE0728: ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/ DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/ For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706: ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706 DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706 |
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Set correct links to download arrier, e.g. TE0706 REV02: TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents Note:
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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