Template Revision 1.1

For modules: rename in this page in  "<series name >- <optional module name>" and put into the All SoM and FPGA Modules Tree

  • <Series Name >  like TE0726
  • <optional module name> like ZynqBerry

Revision changes

  • 1.0 to 1.1
    • add page tree with filter
    • changed style
    • add possibility for key features
    • add posibility for pictures


Expected release in Q2 2022


Key Features

  • SoC/FPGA (Agilex F-Series)
    • Package: R24A(2486A)
    • Device: AGF012,AGF014*
      • with/without HPS*
    • Speed:
      • Transceiver: -1, -2,-3*, **
      • Core: -1, -2,-3,-4*, **
    • Temperature: I, E*, **
  • RAM/Storage
    • DDR4  SODIMM   (4 times)
      • 72-Bit DDR4 with ECC per SODIMM
      • Size: NA*
      • Speed: NA*
    • eMMC
      • Data width: 8Bit
      • size: def. 8GB  (up tp 64 possible)*
    • QSPI boot Flash in single mode (size depends on assembly version)
      • Data width: 4bit
      • size: def. 128MB (up to 256MB possible)*
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • On Board
    • SC CPLD and SIP
      • MAX10: 10M08
      • OSD32MP15x: STM32MP15x(Dual Cortex-A7 and Cortex-M4)  with 512MB DDR3 (16Bit)
    • PLL SI5345
    • Gigabit ETH PHY (Marvell Alaska 88E1512)
    • USB2 HUB
    • USB2 PHY
  • Interface (2 x 400pin COM-HPC connectors by Samtec)
    • PCIe up to  16 lane ( 16x P-Tile (32 Gb/s) +8x E-Tiles (no PCIe))****
    • KR Ethernet (8x E-Tile (29,8 Gb/s))
    • Gbit Ethernet 1x
    • USB2 4x
    • SPI 1x
    • I2C SMB 1x
    • I2C 3x
    • UART 2x (1x Agilex, 1x SC STM32)
    • GPIO 12x (JTAG over GPIO)
  • Power
    • 12V Main
    • 5V Standby
    • 2.0-3.3V RTC
  • Dimension
    • COM-HPC  Client module Size B (120x120mm)
  • Notes
    • * depends on assembly version
    • ** not all combinations are possible
    • *** depends on used U+ Zynq and DDR4 combination
    • **** uses is limited by  U+ Zynq specification