This step guides through the tasks which have to be done inside Intel Quartus. As mentionend in page "Board bring-up overview for TEI0022" this step is for project generation, system setting and output creation. Therefore, the work within this step should be explained in three steps:
The section "Project Creation" describes the basic work to creat a new project. The second section "System Setting" explains the creation of an HPS instance inside the project. And the third section "Output Creation" shows how to create the result output inside Intel Quartus.
This section guides through the project creation:
Now, the following figure should be visible:
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This program generates the files needed to connect and configures the HPS so that it gets connected to the physical board resources.
The basic storage resources the HPS needs are System Memory and SD card access, to communicate the basic interfaces are Uart and i²c.
These files are:
- HPSexample.sopinfo - describes all of the components and connections in your system and
parameterization of each component in the system
- PlattformEditorHPS.qip - The contains paths for all of the files for an IP core
- (hps_isw_)handoff folder - Folder containing board and SoC specific source files for generating the bootloaders
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This section guides through the system setting with the Plattform Designer:
AXI Bridges:
FPGA-to-HPS interface width: Unused
HPS-to-FPGA interface width: Unused
Lightweight HPS-to-FPGA interface width: Unused
Subtab - Memory Parameters:
Memory device speed grade: 800.0 MHz
Total interface width: 32
Row Address width: 16
Column Address width: 10
Memory CAS latency setting: 5
ODT Rtt nominal value: RZQ/6
Memory write CAS latency settings: 5
Subtab - Board Settings:
Board Skews
Maximum CK delay to DIMM/device: 0.03
Maximum DQS delay to DIMM/device: 0.02
Minimum delay difference between CK and DQS: 0.09
Maximum delay difference between CK and DQS: 0.16
Maximum skew within DQS group: 0.01
Maximum skew between DQS groups: 0.08
Maximum skew within address and command bus: 0.03
Add connections via clicking into the circle marked with a red rectangle in th next figure:
hps_0 - h2f_reset → clk_0 - clk_in_reset
clk_0 - clk → hps_0 - f2h_sdram0_data
System → Assign Base Addresses
System → Assign Interrupt Numbers
System → Assign Custom Instruction Opcodes
System → Create Global Reset Network
Close the Plattform Designer by pressing Finish.
This section guides through the output creation:
Click onto the button with three dots (inside the red rectangle) in the opened window as visible in the next figure.