Template Revision 2.12

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"


<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:


        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



-----------------------------------------------------------------------


Note for Download Link of the Scroll ignore macro:


Download PDF version of this document.


Table of Contents

Overview

The Trenz Electronic TEB0835 is a carrier for TE0835 module which is based on Xilinx UltraScale+ RFSoC.

Refer to http://trenz.org/teb0835-info for the current online version of this manual and other available documentation.

Notes :

Key Features

Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modules and mainboards:

  • SoC/FPGA
    • Package: SFVC784
    • Device: ZU2...ZU5*
    • Engine: CG, EG, EV*
    • Speed: -1LI, -2LE,*, **
    • Temperature: I, E,*, **
  • RAM/Storage
    • Low Power DDR4 on PS
      • Data width: 32bit
      • Size: def. 2GB*
      • Speed:***
    • eMMC
      • Data width: 8Bit
      • size: def. 8GB *
    • QSPI boot Flash in dual parallel mode (size depends on assembly version)
      • Data width: 8bit
      • size: def. 128MB *
    • HyperRAM/Flash (optional, default not assembled)
      • size:*
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • On Board
    • Lattice LCMXO2
    • PLL SI5338
    • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
    • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
  • Interface
    • 132 x HP PL I/Os (3 banks)
    • ETH
    • USB
    • 4 GTR (for USB3, Sata, PCIe, DP)
    • MIO for UART
    • MIO for SD
    • MIO for PJTAG
    • JTAG
    • Ctrl
  • Power
    • 3.3V-5V Main Input
    • 3.3V Controller Input
    • Variable Bank IO Power Input
  • Dimension
    • 4 cm x 5 cm
  • Notes
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination


Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension



Block Diagram

add drawIO object here.

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .






Main Components

Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .






  1. SMA Connectors, J1,J3,J5,J7,J9,J11
  2. U.FL (UMCC) Connectors, J2,J4,J6,J8, J10, J12...16
  3. Green LEDs, D6...11
  4. B2B Connector, J18
  5. B2B Connector, J17
  6. Micro SD Card Connector, J28
  7. Reset Push Button, BTN1
  8. Mosfet Transistors
  9. PCIe Connector, J19
  10. Micro USB2.0 Connectors, J29-J30
  11. Gigabit RJ45 Connector, J31
  12. DIP Switch, S1
  13. UEC5 Connector, J22,J24
  14. UCC8 Connector, J23,J25
  15. 4x1 Pin Header, J21
  16. FTDI, U12
  17. Green LEDs, D1...3
  18. 4x1 Pin Header, J20
  19. EEPROM, U15
  20. PCIe Card, J26

Initial Delivery State

Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Storage device name

Content

Notes

EEPROMProgrammed


Configuration Signals

  • Overview of Boot Mode, Reset, Enables.


MODE Signal State

|Boot Mode






MODE[0:3]

Boot ModePin LocationNote

0000

PS_JTAG

JTAGPSJTAG Interface
0001Quad SPI (24b)MIO0...12QSPI 24bit addressing
0010Quad SPI (32b)MIO0...12QSPI 32bit addressing
0011SD0 2.0MIO13...25SD 2.0
0100NANDMIO9...25Requires 8 bit data bus width
0101SD1 2.0MIO31...51SD 2.0
0110eMMCMIO13...22eMMC version 4.5 at 1.8 V
0111USB2.0MIO52...63Only USB2.0
1000PJTAGMIO26...29PJTAG Connection 0 0ption
1001PJTAGMIO12...15PJTAG Connection 1 0ption
1110SD1 LS 3.0MIO39...51SD 3.0 with complaint voltage level shifter




Signal

B2BI/ONote

RESETN

J17- 36InputConnected to Push Button, BTN1


Signals, Interfaces and Pins

Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
Bank 500J1712x Single Ended1.8VMIO14...25
Bank 501J1720x Single Ended1.8VMIO26...51
Bank 505J1718x Single Ended, 9x Differential pairs0.85VEXT_CLKIN_PSMGT, RX/TX0...3
Bank 128J1718x Single Ended, 9x Differential pairs0.9VB128_CLK, RX/TX0...3
Bank 129J1718x Single Ended, 9x Differential pairs0.9VB129_CLK, RX/TX0...3
Bank 65J1824x Single Ended, 12x Differential pairs1.8V
Bank 88J1816x Single Ended, 8x Differential pairs3.3VHD_B88


JTAG Interface

JTAG access to the TEB0835 SoM through B2B connector J17.

JTAG Signal

B2B Connector

TMSJ17-24
TDIJ17-20
TDOJ17-18
TCK

J17-22


Ethernet

U?? Pin Signal NameConnected toSignal DescriptionNote







































































Micro USB2.0

U?? Pin Signal NameConnected toSignal DescriptionNote







































































SMA Connectors

U?? Pin Signal NameConnected toSignal DescriptionNote







































































UMCC Connectors

U?? Pin Signal NameConnected toSignal DescriptionNote







































































UCE5 Connectors

U?? Pin Signal NameConnected toSignal DescriptionNote







































































UCC8 Connectors

U?? Pin Signal NameConnected toSignal DescriptionNote







































































PCIe Card

U?? Pin Signal NameConnected toSignal DescriptionNote







































































MIO Pins

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI



MIO PinConnected toB2BNotes
MIO0...12SPI FLash, U24-U25-Dual SPI FLash
MIO13LED Green, D1-3.3V_CPLD
MIO14...25FPGA Bank 500,U1J1PSMIO
MIO26...27FPGA Bank 501,U1J1PSMIO
MIO28...29CPLD, U31-

UART_TX, UART_RX

MIO30...31FPGA Bank 501, U1J1PSMIO
MIO32...33EEPROM,U23-I2C_SCL, I2C_SDA
MIO34...35FPGA Bank 501,U1J1PSMIO
MIO36Gigabit ETH, U20-ETH_RST
MIO37USB2.0, U11-USB_RST
MIO38...51FPGA Bank 501, U1J1PSMIO
MIO52...62USB2.0, U11-USB
MIO63...77Gigabit ETH, U20-ETH


Test Points

you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test PointSignalB2BNotes
10PWR_PL_OKJ2-120



Test PointSignalConnected toNotes
TP15VB2B, J17
TP2...3GNDGND
TP4ADC0_VCMB2B, J18
TP5ADC1_VCMB2B, J18
TP6USB_VBUSMicro USB2.0, J29
TP7UART0_RXB2B, J17
TP8UART0_TXB2B, J17
TP9ADC2_VCMB2B, J18
TP10ADC3_VCMB2B, J18
TP11ADC4_VCMB2B, J18
TP12ADC5_VCMB2B, J18
TP13ADC6_VCMB2B, J18
TP14ADC7_VCMB2B, J18


On-board Peripherals

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Chip/InterfaceDesignatorNotes
EEPROMU15
FTDIU12
LEDsD1...11
OscillatorsU16, U6
PLL Clock  GeneratorU5



EEPROM

MIO PinSchematicU15 PinNotes










MIO PinI2C AddressDesignatorNotes





LEDs

DesignatorColorConnected toActive LevelNote
D1GreenPG_1.8VHigh
D2GreenPG_3.3VHigh
D3GreenPG_5VHigh
D6...11GreenB2B, J18High


Clock Sources

DesignatorDescriptionFrequencyNote
U6MEMS Oscillator25MHz
U16MEMS Oscillator12MHz
U5PLL Clock GeneratorVariable


Programmable Clock Generator

There is a programmable clock generator on-board (U??) provided in order to generate variable clocks for the module. Programming can be done using I2C via PIN header J??.  The I2C Address is 0x??.

U?? Pin
SignalConnected toDirectionNote
IN3CLK_25MHZ_ROscillator, U6Input
SCLPLL_SCLB2B, J17Input
SDAPLL_SDAB2B, J17In/Out
INTRPLL_INTR_NB2B, J17Output
CLK1B129_CLK1B2B, J17Output
CLK2B128_CLK1B2B, J17Output


Power and Power-On Sequence

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of 3 A for system startup is recommended.

Power Consumption

Power Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies




Power-On Sequence


Create DrawIO object here: Attention if you copy from other page, objects are only linked.


image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


Voltage Monitor Circuit


Create DrawIO object here: Attention if you copy from other page, objects are only linked.


image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed


Power Rails


Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotes

























Bank Voltages

Bank          

Schematic Name

Voltage

Notes






























Board to Board Connectors

  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

The TE0835 has two Samtec Razor Beam on the bottom side.

Technical Specifications

Absolute Maximum Ratings

SymbolsDescriptionMinMaxUnit




V




V




°C




°C


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

ParameterMinMaxUnitsReference Document



VSee ???? datasheets.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



°CSee Xilinx ???? datasheet.



°CSee Xilinx ???? datasheet.


Physical Dimensions

PCB thickness: 1.5 mm.

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .






Currently Offered Variants 

Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

   DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706


Trenz shop TEB0835 overview page
English pageGerman page


Revision History

Hardware Revision History

Set correct links to download  arrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

  • Date format:  YYYY-MM-DD


DateRevisionChangesDocumentation Link
2019-11-29REV01Initial ReleaseREV01


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.





Document Change History

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateRevisionContributorDescription

  • change list

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all

  • --


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