Template Revision 2.12
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
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Table of Contents |
Overview
The Trenz Electronic TEB0835 is a carrier for TE0835 module which is based on Xilinx UltraScale+ RFSoC.
Refer to http://trenz.org/teb0835-info for the current online version of this manual and other available documentation.
Key Features
Note: 'description: Important components and connector or other Features of the module → please sort and indicate assembly options Key Features' must be split into 6 main groups for modules and mainboards: - SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- Modules:
- RAM/Storage
- On Board
- Programmable Clock Generator
- I2C Switch IC
- 9x Green LEDs
- 16x RF Transformation
- Reset Push Buttons
- SDIO Port Expander
- DIP Switch
- Interface
- 10x U.FL Series Connectors
- 6x SMA Connectors
- Micro USB2.0
- 2x UEC5 Connectors
- 2x UCC8 Connectors
- PCIe 8x Connector
- 2x Samtec Razor Beam SS5 (2x80 pol) Board to Board Connectors
- Power
- Dimension
Block Diagram
Main Components
Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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- SMA Connectors, J1,J3,J5,J7,J9,J11
- U.FL (UMCC) Connectors, J2,J4,J6,J8, J10, J12...16
- Green LEDs, D6...11
- B2B Connector, J18
- B2B Connector, J17
- Micro SD Card Connector, J28
- Reset Push Button, BTN1
- Mosfet Transistors
- PCIe Connector, J19
- Micro USB2.0 Connectors, J29-J30
- Gigabit RJ45 Connector, J31
- DIP Switch, S1
- UEC5 Connector, J22,J24
- UCC8 Connector, J23,J25
- 4x1 Pin Header, J21
- FTDI, U12
- Green LEDs, D1...3
- 4x1 Pin Header, J20
- EEPROM, U15
- PCIe Card, J26
Initial Delivery State
Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
Storage device name | Content | Notes |
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EEPROM | Programmed |
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Configuration Signals
- Overview of Boot Mode, Reset, Enables.
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MODE Signal State | |Boot Mode |
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MODE[0:3] | Boot Mode | Pin Location | Note |
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0000 | PS_JTAG | JTAG | PSJTAG Interface | 0001 | Quad SPI (24b) | MIO0...12 | QSPI 24bit addressing | 0010 | Quad SPI (32b) | MIO0...12 | QSPI 32bit addressing | 0011 | SD0 2.0 | MIO13...25 | SD 2.0 | 0100 | NAND | MIO9...25 | Requires 8 bit data bus width | 0101 | SD1 2.0 | MIO31...51 | SD 2.0 | 0110 | eMMC | MIO13...22 | eMMC version 4.5 at 1.8 V | 0111 | USB2.0 | MIO52...63 | Only USB2.0 | 1000 | PJTAG | MIO26...29 | PJTAG Connection 0 0ption | 1001 | PJTAG | MIO12...15 | PJTAG Connection 1 0ption | 1110 | SD1 LS 3.0 | MIO39...51 | SD 3.0 with complaint voltage level shifter |
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Signal | B2B | I/O | Note |
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RESETN | J17- 36 | Input | Connected to Push Button, BTN1 |
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Signals, Interfaces and Pins
Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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Bank 500 | J17 | 12x Single Ended | 1.8V | MIO14...25 | Bank 501 | J17 | 20x Single Ended | 1.8V | MIO26...51 | Bank 505 | J17 | 18x Single Ended, 9x Differential pairs | 0.85V | EXT_CLKIN_PSMGT, RX/TX0...3 | Bank 128 | J17 | 18x Single Ended, 9x Differential pairs | 0.9V | B128_CLK, RX/TX0...3 | Bank 129 | J17 | 18x Single Ended, 9x Differential pairs | 0.9V | B129_CLK, RX/TX0...3 | Bank 65 | J18 | 24x Single Ended, 12x Differential pairs | 1.8V |
| Bank 88 | J18 | 16x Single Ended, 8x Differential pairs | 3.3V | HD_B88 |
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JTAG Interface
JTAG access to the TEB0835 SoM through B2B connector J17.
JTAG Signal | B2B Connector |
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TMS | J17-24 | TDI | J17-20 | TDO | J17-18 | TCK | J17-22 |
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Ethernet
U?? Pin | Signal Name | Connected to | Signal Description | Note |
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Micro USB2.0
U?? Pin | Signal Name | Connected to | Signal Description | Note |
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SMA Connectors
U?? Pin | Signal Name | Connected to | Signal Description | Note |
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UMCC Connectors
U?? Pin | Signal Name | Connected to | Signal Description | Note |
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UCE5 Connectors
U?? Pin | Signal Name | Connected to | Signal Description | Note |
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UCC8 Connectors
U?? Pin | Signal Name | Connected to | Signal Description | Note |
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PCIe Card
U?? Pin | Signal Name | Connected to | Signal Description | Note |
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MIO Pins
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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MIO Pin | Connected to | B2B | Notes |
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MIO0...12 | SPI FLash, U24-U25 | - | Dual SPI FLash | MIO13 | LED Green, D1 | - | 3.3V_CPLD | MIO14...25 | FPGA Bank 500,U1 | J1 | PSMIO | MIO26...27 | FPGA Bank 501,U1 | J1 | PSMIO | MIO28...29 | CPLD, U31 | - | UART_TX, UART_RX | MIO30...31 | FPGA Bank 501, U1 | J1 | PSMIO | MIO32...33 | EEPROM,U23 | - | I2C_SCL, I2C_SDA | MIO34...35 | FPGA Bank 501,U1 | J1 | PSMIO | MIO36 | Gigabit ETH, U20 | - | ETH_RST | MIO37 | USB2.0, U11 | - | USB_RST | MIO38...51 | FPGA Bank 501, U1 | J1 | PSMIO | MIO52...62 | USB2.0, U11 | - | USB | MIO63...77 | Gigabit ETH, U20 | - | ETH |
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Test Points
you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point | Signal | B2B | Notes |
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10 | PWR_PL_OK | J2-120 |
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Test Point | Signal | Connected to | Notes |
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TP1 | 5V | B2B, J17 |
| TP2...3 | GND | GND |
| TP4 | ADC0_VCM | B2B, J18 |
| TP5 | ADC1_VCM | B2B, J18 |
| TP6 | USB_VBUS | Micro USB2.0, J29 |
| TP7 | UART0_RX | B2B, J17 |
| TP8 | UART0_TX | B2B, J17 |
| TP9 | ADC2_VCM | B2B, J18 |
| TP10 | ADC3_VCM | B2B, J18 |
| TP11 | ADC4_VCM | B2B, J18 |
| TP12 | ADC5_VCM | B2B, J18 |
| TP13 | ADC6_VCM | B2B, J18 |
| TP14 | ADC7_VCM | B2B, J18 |
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On-board Peripherals
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
Chip/Interface | Designator | Notes |
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EEPROM | U15 |
| FTDI | U12 |
| LEDs | D1...11 |
| Oscillators | U16, U6 |
| PLL Clock Generator | U5 |
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EEPROM
MIO Pin | Schematic | U15 Pin | Notes |
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MIO Pin | I2C Address | Designator | Notes |
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LEDs
Designator | Color | Connected to | Active Level | Note |
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D1 | Green | PG_1.8V | High |
| D2 | Green | PG_3.3V | High |
| D3 | Green | PG_5V | High |
| D6...11 | Green | B2B, J18 | High |
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Clock Sources
Designator | Description | Frequency | Note |
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U6 | MEMS Oscillator | 25MHz |
| U16 | MEMS Oscillator | 12MHz |
| U5 | PLL Clock Generator | Variable |
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Programmable Clock Generator
There is a programmable clock generator on-board (U??) provided in order to generate variable clocks for the module. Programming can be done using I2C via PIN header J??. The I2C Address is 0x??.
U?? Pin
| Signal | Connected to | Direction | Note |
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IN3 | CLK_25MHZ_R | Oscillator, U6 | Input |
| SCL | PLL_SCL | B2B, J17 | Input |
| SDA | PLL_SDA | B2B, J17 | In/Out |
| INTR | PLL_INTR_N | B2B, J17 | Output |
| CLK1 | B129_CLK1 | B2B, J17 | Output |
| CLK2 | B128_CLK1 | B2B, J17 | Output |
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Power and Power-On Sequence
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of 3 A for system startup is recommended.
Power Consumption
Power Input Pin | Typical Current |
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VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
Power-On Sequence
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
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Voltage Monitor Circuit
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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Power Rails
Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
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Bank Voltages
Board to Board Connectors
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
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The TE0835 has two Samtec Razor Beam on the bottom side.
Technical Specifications
Absolute Maximum Ratings
Symbols | Description | Min | Max | Unit |
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| V |
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Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
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| V | See ???? datasheets. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| V | See Xilinx ???? datasheet. |
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| °C | See Xilinx ???? datasheet. |
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| °C | See Xilinx ???? datasheet. |
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Physical Dimensions
PCB thickness: 1.5 mm.
Currently Offered Variants
Revision History
Hardware Revision History
Date | Revision | Changes | Documentation Link |
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2019-11-29 | REV01 | Initial Release | REV01 |
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Date | Revision | Contributor | Description |
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Disclaimer