Template Revision 1.8 - on construction Design Name always "TE Series Name" + optional CPLD Name + "CPLD" |
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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware |
Table of contents |
Firmware for system controller with designator U41: 10M08SAU169C8G
See Document Change History
Name / opt. VHD Name | Direction | Pin | Bank Power | Description |
---|---|---|---|---|
BOOTSEL2 / BOOTSEL2 | out | L10 | +3.3V | Boot Select Bit 2 |
JTAGSEL0 / JTAGSEL0 | in | F9 | +3.3V_MAX10 | Select JTAG Connection |
JTAGSEL1 / JTAGSEL1 | in | E9 | +3.3V_MAX10 | Select JTAG Connection |
FTDI_JTAG_TC/SK / FTDI_TCK | in | G2 | +3.3V_MAX10 | FTDI JTAG TCK |
FTDI_JTAG_TDO/DI / FTDI_TDI | in | F6 | +3.3V_MAX10 | FTDI JTAG TDI |
FTDI_JTAG_TMS/CS / FTDI_TMS | in | G1 | +3.3V_MAX10 | FTDI JTAG TCK |
HPS_TDO / HPS_TDO | in | J6 | +3.3V | HPS JTAG TDO |
FPGA_TDI / FPGA_TDO | in | J1 | +3.3V | FPGA JTAG TDO |
FMC_TDO / FMC_TDO | in | M10 | +3.3V | FMC JTAG TDO |
FTDI_JTAG_TDI/DO / FTDI_TDO | out | F5 | +3.3V_MAX10 | FTDI JTAG TDO |
HPS_TCK / HPS_TCK | out | K1 | +3.3V | HPS JTAG TCK |
HPS_TDI / HPS_TDI | out | M4 | +3.3V | HPS JTAG TDI |
HPS_TMS / HPS_TMS | out | M7 | +3.3V | HPS JTAG TMS |
FPGA_TCK / FPGA_TCK | out | K2 | +3.3V | HPS JTAG TCK |
FPGA_TDO / FPGA_TDI | out | L2 | +3.3V | FPGA JTAG TDI |
FPGA_TMS / FPGA_TMS | out | J2 | +3.3V | FPGA JTAG TMS |
FMC_TCK/ FMC_TCK | out | M8 | +3.3V | FMC JTAG TCK |
FMC_TDI / FMC_TDI | out | M9 | +3.3V | FMC JTAG TDI |
FMC_TMS / FMC_TMS | out | M11 | +3.3V | FMC JTAG TMS |
HPS_RST#_SW / HPS_RSTn_SW | in | J5 | +3.3V | Reset Button |
HPS_RST#_BO / HPS_RSTn_BO | in | K6 | +3.3V | Brown Out Detection |
HPS_WARM_RST#_SW / HPS_WARM_RSTn_SW | in | K5 | +3.3V | Warm Reset Button |
FPGA_RST#_SW / FPGA_RSTn_SW | in | B4 | +3.3V_MAX10 | FPGA Reset Button |
HPS_RST# / HPS_RSTn | out | L11 | +3.3V | HPS Reset |
HPS_WARM_RST# / HPS_WARM_RSTn | out | M3 | +3.3V | HPS Warm Reset |
FPGA_RST# / FPGA_RSTn | out | L13 | VDD_DDR_FPGA | FPGA Reset |
VID0_SW / VID0_SW | in | F8 | +3.3V_MAX10 | Power Selection Pin 0 for FMC Voltage |
VID1_SW / VID1_SW | in | E8 | +3.3V_MAX10 | Power Selection Pin 1 for FMC Voltage |
VID2_SW / VID2_SW | in | D8 | +3.3V_MAX10 | Power Selection Pin 2 for FMC Voltage |
CPU_GPIO_0 / CPU_GPIO0 | in | N10 | +3.3V | CPU GPIO 0 (used for automatic power selection for FMC Voltage) |
CPU_GPIO_1 / CPU_GPIO1 | in | N9 | +3.3V | CPU GPIO 1 (used for automatic power selection for FMC Voltage) |
CPU_GPIO_2 / CPU_GPIO2 | in | N11 | +3.3V | CPU GPIO 2 (used for automatic power selection for FMC Voltage) |
VID0 / VID0 | out | B2 | +3.3V_MAX10 | Power Selection Pin 0 for FMC Voltage at U43 |
VID1 / VID1 | out | C2 | +3.3V_MAX10 | Power Selection Pin 1 for FMC Voltage at U43 |
VID2 / VID2 | out | F4 | +3.3V_MAX10 | Power Selection Pin 2 for FMC Voltage at U43 |
PWR_SEL / PWR_SEL | out | E4 | +3.3V_MAX10 | Power Selection for Cyclone V FMC VCCPD at U37 |
USER_BTN_SW / USER_BTN_SW | in | B3 | +3.3V_MAX10 | User Button |
USER_BTN_FPGA / USER_BTN_FPGA | out | G12 | VDD_DDR_FPGA | FPGA User Button |
BDBUS0 / FTDI_RXD | in | D1 | +3.3V_MAX10 | FTDI UART RXD |
FPGA_GPIO_1 / FPGA_IO1 | in | J10 | VDD_DDR_FPGA | FPGA IO 1 |
FPGA_GPIO_0 / FPGA_IO0 | out | K11 | VDD_DDR_FPGA | FPGA IO 0 |
BDBUS1 / FTDI_TXD | out | C1 | +3.3V_MAX10 | FTDI UART TXD |
CPU_GPIO_4 / CPU_GPIO4 | in | H4 | +3.3V | CPU GPIO 4 (used for fan control) |
FAN_EN / FAN_EN | out | D13 | +3.3V_MAX10 | Fan Control |
MODE_VCC / MODE_DCDC_VCC | out | D9 | +3.3V_MAX10 | VCC DCDC Mode Selection |
MODE / MODE_DCDC_5V | out | A11 | +3.3V_MAX10 | +5.0 V DCDC Mode Selection |
MODE_DDR_FPGA / MODE_DCDC_FPGA | out | E10 | +3.3V_MAX10 | FPGA DDR Power DCDC Mode Selection |
MODE_DDR_HPS / MODE_DCDC_HPS | out | F10 | +3.3V_MAX10 | HPS DDR Power DCDC Mode Selection |
PG_+5.0V / PG_5V0 | in | A8 | +3.3V_MAX10 | +5.0 V Power Good |
PG_VCC / PG_VCC | in | B11 | +3.3V_MAX10 | VCC Power Good |
PG_+2.5V / PG_2V5 | in | C11 | +3.3V_MAX10 | +2.5 V Power Good |
PG_+1.8V / PG_1V8 | in | D11 | +3.3V_MAX10 | +1.8 V Power Good |
PG_+3.3V / PG_3V3 | in | B12 | +3.3V_MAX10 | +3.3 V Power Good |
EN_VCC / EN_VCC | out | A10 | +3.3V_MAX10 | VCC Power Enable |
EN_+2.5V / EN_2V5 | out | A12 | +3.3V_MAX10 | +2.5 V Power Enable |
EN_+1.8V / EN_1V8 | out | D12 | +3.3V_MAX10 | +1.8 V Power Enable |
LED_VCC / LED_VCC | out | F12 | +3.3V_MAX10 | VCC Power Led |
EN_+3.3V / EN_3V3 | out | B13 | +3.3V_MAX10 | +3.3 V Power Enable |
EN_+0.9V / EN_0V9 | out | F1 | +3.3V_MAX10 | +0.9 V Power Enable |
LED_+1.8 V / LED_1V8 | out | H2 | +3.3V_MAX10 | +1.8 V Power Led |
EN_DDR_HPS / EN_DDR_HPS | out | F13 | +3.3V_MAX10 | HPS DDR Power Enable |
EN_DDR_FPGA / EN_DDR_FPGA | out | E13 | +3.3V_MAX10 | FPGA DDR Power Enable |
CPU_GPIO_3 / CPU_GPIO3 | in | L1 | +3.3V | CPU GPIO 3 (used for FMC Power Enable) |
FMC_PRSNT_M2C# / FMC_PRSNT_M2Cn | in | J7 | +3.3V | FMC Card Detection from FMC Connector |
EN_FMC_+12.0V / EN_FMC_12V | out | C12 | +3.3V_MAX10 | +12.0 V FMC Power Enable |
EN_FMC / EN_FMC | out | E1 | +3.3V_MAX10 | Power Enable for FMC Voltage at U43 |
PWR_SWT_EN / PWR_VCCPD_EN | out | C10 | +3.3V_MAX10 | Power Enable for Cyclone V VCCPD Voltage |
EN_FMC_+3.3V / EN_FMC_3V3 | out | C13 | +3.3V_MAX10 | +3.3 V FMC Power Enable |
FMC_PG_C2M / FMC_PG_C2M | out | K7 | +3.3V | FMC Power Good Signal to FMC Connector |
POK_FMC / POK_FMC | in | E3 | +3.3V_MAX10 | Power Good for FMC Voltage at U43 |
PG_VDD_FPGA / PG_VDD_FPGA | in | E12 | +3.3V_MAX10 | FPGA VDD DDR Power Good |
PG_VDD_HPS / PG_VDD_HPS | in | G10 | +3.3V_MAX10 | HPS VDD DDR Power Good |
LED_FMC_VADJ / LED_FMC_VADJ | out | C9 | +3.3V_MAX10 | Power Good Led for FMC Voltage at U43 |
LED_VDD_DDR_FPGA / LED_VDD_DDR_FPGA | out | E6 | +3.3V_MAX10 | FPGA DDR VDD Power Good Led |
LED_VTT_DDR_FPGA / LED_VTT_DDR_FPGA | out | D6 | +3.3V_MAX10 | FPGA DDR VTT Power Good Led |
LED_VDD_DDR_HPS / LED_VDD_DDR_HPS | out | H3 | +3.3V_MAX10 | HPS DDR VDD Power Good Led |
LED_VTT_DDR_HPS / LED_VTT_DDR_HPS | out | G4 | +3.3V_MAX10 | HPS DDR VTT Power Good Led |
JTAGEN / | in | E5 | +3.3V_MAX10 | Select JTAG Connection |
EN_+5.0V / EN_5V0 | out | A7 | +3.3V_MAX10 | +5.0 V Power Enable |
PG_VTT_FPGA / PG_VTT_FPGA | in | B10 | +3.3V_MAX10 | FPGA VTT DDR Power Good |
PG_VTT_HPS / PG_VTT_HPS | in/out | B5 | +3.3V_MAX10 | HPS VTT DDR Power Good |
STATUS / | out | H1 | +3.3V_MAX10 | / currently_not_used |
BDBUS2 / | in/out | B1 | +3.3V_MAX10 | / currently_not_used |
BCBUS2 / | in/out | A9 | +3.3V_MAX10 | / currently_not_used |
DEVCLRn / | in | B9 | +3.3V_MAX10 | / currently_not_used |
BDBUS7 / | in/out | A6 | +3.3V_MAX10 | / currently_not_used |
BCBUS1 / | in/out | B6 | +3.3V_MAX10 | / currently_not_used |
BDBUS5 / | in/out | A4 | +3.3V_MAX10 | / currently_not_used |
BDBUS4 / | in/out | A3 | +3.3V_MAX10 | / currently_not_used |
nSTATUS / | in/out | C4 | +3.3V_MAX10 | / currently_not_used |
CONF_DONE / | in/out | C5 | +3.3V_MAX10 | / currently_not_used |
BDBUS3 / | in/out | A2 | +3.3V_MAX10 | / currently_not_used |
BDBUS6 / | in/out | A5 | +3.3V_MAX10 | / currently_not_used |
CLK_MAX10 / | in | H6 | +3.3V | / currently_not_used |
ETH_RST / | out | G5 | +3.3V | / currently_not_used |
USB_RST | out | H5 | +3.3V | / currently_not_used |
USER_BTN_HPS / | out | M2 | +3.3V | / currently_not_used |
nCONFIG_I / | in | M1 | +3.3V | / currently_not_used |
MSEL1 / | in/out | N3 | +3.3V | / currently_not_used |
MSEL2 / | in/out | N2 | +3.3V | / currently_not_used |
USB_HUB_RST / | out | L3 | +3.3V | / currently_not_used |
FPGA_GPIO_9 / | in/out | K10 | VDD_DDR_FPGA | / currently_not_used |
FPGA_GPIO_3 / | in/out | L12 | VDD_DDR_FPGA | / currently_not_used |
FPGA_GPIO_2 / | in/out | K12 | VDD_DDR_FPGA | / currently_not_used |
FPGA_GPIO_11 / | in/out | J12 | VDD_DDR_FPGA | / currently_not_used |
FPGA_GPIO_8 / | in/out | J9 | VDD_DDR_FPGA | / currently_not_used |
FPGA_GPIO_12 / | in/out | H10 | VDD_DDR_FPGA | / currently_not_used |
FPGA_GPIO_10 / | in/out | J13 | VDD_DDR_FPGA | / currently_not_used |
FPGA_GPIO_5 / | in/out | H13 | VDD_DDR_FPGA | / currently_not_used |
FPGA_GPIO_7 / | in/out | H9 | VDD_DDR_FPGA | / currently_not_used |
FPGA_GPIO_6 / | in/out | H8 | VDD_DDR_FPGA | / currently_not_used |
FPGA_GPIO_4 / | in/out | G13 | VDD_DDR_FPGA | / currently_not_used |
nSTATUS_I / | in | L4 | +3.3V | / currently_not_used |
CONF_DONE_I / | in | L5 | +3.3V | / currently_not_used |
HPS_TRST# / | out | M5 | +3.3V | / currently_not_used |
MSEL0 / | out | N5 | +3.3V | / currently_not_used |
MSEL3 / | out | N4 | +3.3V | / currently_not_used |
MSEL4 / | out | N6 | +3.3V | / currently_not_used |
CLKSEL0 / | out | N8 | +3.3V | / currently_not_used |
CLKSEL1 / | out | N7 | +3.3V | / currently_not_used |
FMC_TRST# / | out | M12 | +3.3V | / currently_not_used |
FMC_SDA / | in/out | M13 | +3.3V | / currently_not_used |
HPS_SPI_SS/BOOTSEL0 | in/out | K8 | +3.3V | / currently_not_used |
QSPI_CS/BOOTSEL1 | in/out | J8 | +3.3V | / currently_not_used |
FMC_SCL / | in/out | N12 | +3.3V | / currently_not_used |
The mode signals are connected to "1".
Signal | State | Description |
---|---|---|
MODE_DCDC_VCC, MODE_DCDC_5V | 1 | Forced Continous Mode |
0 | Discontinous Mode | |
MODE_DCDC_FPGA, MODE_DCDC_HPS | 1 | Pulse-Skipping Mode for VDD |
0 | Forced Continous Mode for VDD |
Can be enabled/disabled through the Intel Cyclone V HPS "CPU_GPIO4".
The power is enabled if signal "CPU_GPIO3" is set to "1" and there is an FMC card. Then, the +12.0 V level is enabled. After that, the adjustable voltage is enabled. Finally, the +3.3 V level is enabled. Then, the signal "FMC_PG_C2M" is asserted.
The FTDI JTAG is connected to the Intel MAX10, the Intel Cyclone V HPS and Fabric and to the FMC Connector according to the following table.
JTAG_SEL0 | JTAG_SEL1 | JTAGEN | JTAG Connection |
---|---|---|---|
X | X | 1 - (ON) | Intel MAX10 |
0 - (ON) | 0 - (ON) | 0 - (OFF) | Cyclone V HPS |
0 - (ON) | 1 - (OFF) | 0 - (OFF) | Cyclone V FPGA |
1 - (OFF) | 0 - (ON) | 0 - (OFF) | FMC |
The leds signals their power good status.
The second channel of the JTAG FTDI interface delievers an UART connection to the Intel Cyclone V fabric.
The User Button is connected to the FPGA.
The power sequencing is handled inside the system controller according to the next figure.
The FMC power sequencing depends on the assertion through the signals "CPU_GPIO3" and "FMC_PRSNT_M2Cn". If both of them are asserted, the +12.0 V level starts, followed by the adjustabel voltage level with the according pre-driver voltage and finally, the +3.3 V level is started.
The FMC adjustable voltage selection can be done manually by the switches or automatically by the Intel Cyclone V HPS. The choice is done via the switches according to the next table. The voltage for the Intel Cyclone V HPS pre-driver is selected according to the voltage setting.
S8-C | S8-B | S8-A | Voltage | Setting |
---|---|---|---|---|
ON | ON | ON | 3.3 V | Manual |
ON | ON | OFF | 2.5 V | Manual |
ON | OFF | ON | 1.8 V | Manual |
ON | OFF | OFF | 1.5 V | Manual |
OFF | ON | ON | 1.25 V | Manual |
OFF | ON | OFF | 1.2 V | Manual |
OFF | OFF | ON | 0.8 V | Manual |
OFF | OFF | OFF | CPU-dependent | CPU |
The reset buttons are connected via the system controller to the according reset locations. That means that, if the reset button S1 or the brown-out detection is asserted, the Cyclone V should be reseted. If the warm reset button S3 is asserted, the Cyclone V should be warm reseted. If the FPGA reset button S4 is asserted, the FPGA could be reseted.
CPLD REV01 to REV02
To get content of older revision got to "Change History" of this page and select older document revision number.
|
Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
---|---|---|---|---|---|
Work in progress | |||||
2020-02-19 | REV02 | REV02 | Initial release | ||
All |