Template Revision 2.7 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" |
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Important General Note:
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Table of contents |
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Xilinx IBERT with TE0808 Starterkit (TEBF0808 Carrier).
Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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Note: Design contains also Board Part Files for TE0808 only configuration, this boart part files are not used for this reference design.
Design supports following carriers:
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Additional HW Requirements:
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For general structure and of the reference design, see Project Delivery - AMD devices
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Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
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For basic board setup, LEDs... see: TEBF0808 Getting Started
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Optional for Boot.bin on QSPI Flash and image.ub on SD.
Not used on this Example.
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Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
TODO picture |
TODO mapping table
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*Note: IBERT is used as RTL IP, TOP entity is modified version from Xilinx eIBERT example export |
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Activated interfaces:
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
# file: ibert_ultrascale_gth_0.xdc #################################################################################### ## ____ ____ ## / /\/ / ## /___/ \ / Vendor: Xilinx ## \ \ \/ Version : 2017.1 ## \ \ Application : IBERT Ultrascale ## / / Filename : example_ip_ibert_ultrascale_gth_0.xdc ## /___/ /\ ## \ \ / \ ## \___\/\___\ ## ## ## ## Generated by Xilinx IBERT ##************************************************************************** ## ## TX/RX out clock clock constraints ## # GT X0Y4 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[0].u_q/CH[0].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks] set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[0].u_q/CH[0].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks] # GT X0Y5 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[0].u_q/CH[1].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks] set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[0].u_q/CH[1].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks] # GT X0Y6 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[0].u_q/CH[2].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks] set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[0].u_q/CH[2].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks] # GT X0Y7 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[0].u_q/CH[3].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks] set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[0].u_q/CH[3].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks] # GT X0Y4 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[1].u_q/CH[0].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks] set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[1].u_q/CH[0].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks] # GT X0Y5 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[1].u_q/CH[1].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks] set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[1].u_q/CH[1].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks] # GT X0Y6 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[1].u_q/CH[2].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks] set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[1].u_q/CH[2].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks] # GT X0Y7 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[1].u_q/CH[3].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks] set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[1].u_q/CH[3].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks] # GT X0Y8 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[2].u_q/CH[0].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks] set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[2].u_q/CH[0].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks] # GT X0Y9 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[2].u_q/CH[1].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks] set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[2].u_q/CH[1].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks] # GT X0Y10 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[2].u_q/CH[2].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks] set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[2].u_q/CH[2].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks] # GT X0Y11 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[2].u_q/CH[3].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks] set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[2].u_q/CH[3].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks] # GT X0Y12 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[3].u_q/CH[0].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks] set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[3].u_q/CH[0].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks] # GT X0Y13 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[3].u_q/CH[1].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks] set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[3].u_q/CH[1].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks] # GT X0Y14 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[3].u_q/CH[2].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks] set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[3].u_q/CH[2].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks] # GT X0Y15 set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[3].u_q/CH[3].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks] set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[3].u_q/CH[3].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks] |
# file: ibert_ultrascale_gth_0.xdc #################################################################################### ## ____ ____ ## / /\/ / ## /___/ \ / Vendor: Xilinx ## \ \ \/ Version : 2012.3 ## \ \ Application : IBERT Ultrascale ## / / Filename : example_ibert_ultrascale_gth_0.xdc ## /___/ /\ ## \ \ / \ ## \___\/\___\ ## ## ## ## Generated by Xilinx IBERT 7Series ##************************************************************************** ## ## Icon Constraints ## create_clock -name D_CLK -period 10.0 [get_ports gth_sysclkp_i] set_clock_groups -group [get_clocks D_CLK -include_generated_clocks] -asynchronous set_property C_CLK_INPUT_FREQ_HZ 100000000 [get_debug_cores dbg_hub] set_property C_ENABLE_CLK_DIVIDER true [get_debug_cores dbg_hub] ##gth_refclk lock constraints ## set_property PACKAGE_PIN F25 [get_ports gth_refclk0p_i[0]] set_property PACKAGE_PIN F26 [get_ports gth_refclk0n_i[0]] set_property PACKAGE_PIN D25 [get_ports gth_refclk1p_i[0]] set_property PACKAGE_PIN D26 [get_ports gth_refclk1n_i[0]] set_property PACKAGE_PIN R8 [get_ports gth_refclk0p_i[1]] set_property PACKAGE_PIN R7 [get_ports gth_refclk0n_i[1]] set_property PACKAGE_PIN N8 [get_ports gth_refclk1p_i[1]] set_property PACKAGE_PIN N7 [get_ports gth_refclk1n_i[1]] set_property PACKAGE_PIN L8 [get_ports gth_refclk0p_i[2]] set_property PACKAGE_PIN L7 [get_ports gth_refclk0n_i[2]] set_property PACKAGE_PIN J8 [get_ports gth_refclk1p_i[2]] set_property PACKAGE_PIN J7 [get_ports gth_refclk1n_i[2]] set_property PACKAGE_PIN G8 [get_ports gth_refclk0p_i[3]] set_property PACKAGE_PIN G7 [get_ports gth_refclk0n_i[3]] set_property PACKAGE_PIN E8 [get_ports gth_refclk1p_i[3]] set_property PACKAGE_PIN E7 [get_ports gth_refclk1n_i[3]] ## ## Refclk constraints ## create_clock -name gth_refclk0_1 -period 8.0 [get_ports gth_refclk0p_i[0]] create_clock -name gth_refclk1_1 -period 8.0 [get_ports gth_refclk1p_i[0]] set_clock_groups -group [get_clocks gth_refclk0_1 -include_generated_clocks] -asynchronous set_clock_groups -group [get_clocks gth_refclk1_1 -include_generated_clocks] -asynchronous create_clock -name gth_refclk0_3 -period 8.0 [get_ports gth_refclk0p_i[1]] create_clock -name gth_refclk1_3 -period 8.0 [get_ports gth_refclk1p_i[1]] set_clock_groups -group [get_clocks gth_refclk0_3 -include_generated_clocks] -asynchronous set_clock_groups -group [get_clocks gth_refclk1_3 -include_generated_clocks] -asynchronous create_clock -name gth_refclk0_4 -period 8.0 [get_ports gth_refclk0p_i[2]] create_clock -name gth_refclk1_4 -period 8.0 [get_ports gth_refclk1p_i[2]] set_clock_groups -group [get_clocks gth_refclk0_4 -include_generated_clocks] -asynchronous set_clock_groups -group [get_clocks gth_refclk1_4 -include_generated_clocks] -asynchronous create_clock -name gth_refclk0_5 -period 8.0 [get_ports gth_refclk0p_i[3]] create_clock -name gth_refclk1_5 -period 8.0 [get_ports gth_refclk1p_i[3]] set_clock_groups -group [get_clocks gth_refclk0_5 -include_generated_clocks] -asynchronous set_clock_groups -group [get_clocks gth_refclk1_5 -include_generated_clocks] -asynchronous ## ## System clock pin locs and timing constraints ## #set_property PACKAGE_PIN AH7 [get_ports gth_sysclkp_i] #set_property IOSTANDARD DIFF_SSTL15 [get_ports gth_sysclkp_i] |
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For SDK project creation, follow instructions from:
---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2019.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2019.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynq_fsbl_flashTE modified 2019.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2019.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin. |
SDK template in ./sw_lib/sw_apps/ available.
TE modified 2019.2 FSBL
General:
Module Specific:
TE modified 2019.2 FSBL
General:
Hello TE0808 IBERTis a Xilinx Hello World example as endless loop instead of one console output.
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File location <design name>/misc/Si5345/Si5345-*.slabtimeproj
General documentation how you work with these project will be available on Si5345
To get content of older revision got to "Change History" of this page and select older document revision number.
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