Template Revision 2.7 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"


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Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):


        Create DrawIO object here: Attention if you copy from other page, use


        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

      • ExampleComment
        12



  • ...


Table of contents

Overview

Notes :

Xilinx IBERT with TE0808 Starterkit (TEBF0808 Carrier).

Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.

Key Features

Notes :

  • Add basic key futures, which can be tested with the design


  • Vitis/Vivado 2019.2
  • TEBF0808
  • PL IBERT
  • Modified FSBL for Si5338 programming
  • Special FSBL for QSPI Programming

Revision History

Notes :

  • add every update file on the download
  • add design changes on description


DateVivadoProject BuiltAuthorsDescription
2020-09-292019.2TE0808-test_board-vivado_2019.2-build_15_20200929070725.zip
TE0808-test_board_noprebuilt-vivado_2019.2-build_15_20200929070740.zip
John Hartfiel
  • new assembly variants
2020-03-252019.2???John Hartfiel
  • 2019.2 initial release


Release Notes and Know Issues

Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed


IssuesDescriptionWorkaround/SolutionTo be fixed version
--------


Requirements

Software

Notes :

  • list of software which was used to generate the design


SoftwareVersionNote
Vitis2019.2needed, Vivado is included into Vitis installation
PetaLinux2019.2needed
SI ClockBuilder Pro---optional


Hardware

Notes :

  • list of software which was used to generate the design

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0808-ES1          es1_2gb      REV03|REV02 2GB      64MB       NA         NA               Not longer supported by vivado       
TE0808-ES2          es2_2gb      REV04|REV03 2GB      64MB       NA         NA               Not longer supported by vivado                   
TE0808-2ES2         2es2_2gb     REV04|REV03 2GB      64MB       NA         NA               Not longer supported by vivado                
TE0808-04-09EG-1EA  9eg_1e_2gb   REV04       2GB      64MB       NA         NA               
TE0808-04-09EG-1EB  9eg_1e_4gb   REV04       4GB      64MB       NA         NA               
TE0808-04-09EG-1ED  9eg_1e_4gb   REV04       4GB      64MB       NA         1 mm connectors
TE0808-04-09EG-2IB  9eg_2i_4gb   REV04       4GB      64MB       NA         NA               
TE0808-04-15EG-1EB  15eg_1e_4gb  REV04       4GB      64MB       NA         NA               
TE0808-04-09EG-1EE  9eg_1e_4gb   REV04       4GB      128MB      NA         NA               
TE0808-04-09EG-1EL  9eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectors
TE0808-04-09EG-2IE  9eg_2i_4gb   REV04       4GB      128MB      NA         NA               
TE0808-04-15EG-1EE  15eg_1e_4gb  REV04       4GB      128MB      NA         NA               
TE0808-04-06EG-1EE  6eg_1e_4gb   REV04       4GB      128MB      NA         NA               
TE0808-04-06EG-1E3  6eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectors
TE0808-04-6GI21-L   6eg_2i_4gb   REV04       4GB      128MB      NA         1 mm connectors
TE0808-04-6GI21-A   6eg_2i_4gb   REV04       4GB      128MB      NA         NA               
TE0808-04-6BI21-A   6eg_1i_4gb   REV04       4GB      128MB      NA         NA               
TE0808-04-9GI21-A   9eg_2i_4gb   REV04       4GB      128MB      NA         NA               
TE0808-04-9BE21-A   9eg_1e_4gb   REV04       4GB      128MB      NA         NA               
TE0808-04-6BE21-L   6eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectors
TE0808-04-6BE21-A   6eg_1e_4gb   REV04       4GB      128MB      NA         NA               
TE0808-04-9BE21-L   9eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectors
TE0808-04-BBE21-A   15eg_1e_4gb  REV04       4GB      128MB      NA         NA               
TE0808-04-6BI21-X6eg_1i_4gbREV04       4GB128MBNANAU41 replaced with schottky diodes
TE0808-05-6BE21-A   6eg_1e_4gb   REV05       4GB      128MB      NA         NA               NA                                     
TE0808-05-6BI21-D   6eg_1i_4gb   REV05       4GB      128MB      NA         1 mm connectorsSoC without encryption               
TE0808-05-6BI21-X   6eg_1i_4gb   REV05       4GB      128MB      NA         NA               U41 replaced with schottky diodes    
TE0808-05-6BI41-X   6eg_1i_8gb   REV05       8GB      128MB      NA         NA               U41 replaced with schottky diodes    
TE0808-05-9BE21-A   9eg_1e_4gb   REV05       4GB      128MB      NA         NA               NA                                     
TE0808-05-9BE21-L   9eg_1e_4gb   REV05       4GB      128MB      NA         1 mm connectorsNA                                     
TE0808-05-9BI41-X   9eg_1i_8gb   REV05       8GB      128MB      NA         NA               U41 replaced with schottky diodes    
TE0808-05-9GI21-A   9eg_2i_4gb   REV05       4GB      128MB      NA         NA               NA                                     
TE0808-05-9GI21-C   9eg_2i_4gb   REV05       4GB      128MB      NA         NA               SoC without encryption               
TE0808-05-BBE21-A   15eg_1e_4gb  REV05       4GB      128MB      NA         NA               NA                                     
TE0808-05-BBE21-L   15eg_1e_4gb  REV05       4GB      128MB      NA         1 mm connectorsNA      


Note: Design contains also Board Part Files for TE0808 only configuration, this boart part files are not used for this reference design.

Design supports following carriers:

Carrier ModelNotes
TEBF0808Used as reference carrier. Important: CPLD Firmware REV07 or newer is recommended


Additional HW Requirements:

Additional HardwareNotes
Heat Sink for the SoCImportant!
FMC Loopback KarteOptional HW
SFP+ Loopback Adapter
Firefly cableloopback possible with second connector on the carrier
PCIe CardOptional HW
SD cardwith fat32 partiton


Content

Notes :

  • content of the zip file

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
<design name>/hdl
Vivado Project will be generated by TE Scripts
Vitis<design name>/sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration


Additional Sources

TypeLocationNotes
SI5345<design name>/misc/Si5345SI5345 Project with current PLL Configuration


Prebuilt

Notes :

  • prebuilt files
  • Template Table:

    • File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems




File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Design Flow

Notes :
  • Basic Design Steps

  • Add/ Remove project specific description


Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
                Important: Use Board Part Files, which ends with *_tebf0808
  5. Create XSA and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Generate Programming Files with Vitis
    1. Run on Vivado TCL: TE::sw_run_vitis -all
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
      Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis

Launch

Note:

  • Programming and Startup procedure

For basic board setup, LEDs... see: TEBF0808 Getting Started

Programming

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder
      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_ibert
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
  4. Set Boot Mode to QSPI-Boot
    1. Depends on Carrier, see carrier TRM.
    2. TEBF0808 change automatically the Boot Mode to SD, if SD is insered, optional CPLD Firmware without Boot Mode changing for mircoSD Slot is available on the download area

SD

  1. Copy  Boot.bin on SD-Card
  2. Set Boot Mode to SD-Boot.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section TE0808 StarterKit#Programming
  2. Connect UART USB (JTAG XMOD)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)
    Note: See TRM of the Carrier, which is used.
  4. (Optional) Connect MGT loopback adapter
    Note: 1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from SD into OCM, 2. FSBL loads  application from SD/QSPI into DDR.

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Console: 'Hello IBERT (TE0808) (Loop: %i) * is running in endless loop

Vivado Hardware Manager

Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only

    SI5338_CLK0 Counter: 

    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).

TODO picture


TODO mapping table

System Design - Vivado

Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

Block Design

*Note: IBERT is used as RTL IP, TOP entity is  modified version from Xilinx eIBERT example export


PS Interfaces

Note:

  • optional for Zynq / ZynqMP only

  • add basic PS configuration

Activated interfaces:

TypeNote
DDR
QSPIMIO
SD1MIO
I2C0MIO
UART0MIO
GPIO0MIO
SWDT0..1
TTC0..3


Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

# file: ibert_ultrascale_gth_0.xdc
####################################################################################
##   ____  ____ 
##  /   /\/   /
## /___/  \  /    Vendor: Xilinx
## \   \   \/     Version : 2017.1
##  \   \         Application : IBERT Ultrascale
##  /   /         Filename : example_ip_ibert_ultrascale_gth_0.xdc
## /___/   /\     
## \   \  /  \ 
##  \___\/\___\
##
##
## 
## Generated by Xilinx IBERT 
##**************************************************************************
##
## TX/RX out clock clock constraints
##
# GT X0Y4
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[0].u_q/CH[0].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[0].u_q/CH[0].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks]
# GT X0Y5
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[0].u_q/CH[1].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[0].u_q/CH[1].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks]
# GT X0Y6
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[0].u_q/CH[2].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[0].u_q/CH[2].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks]
# GT X0Y7
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[0].u_q/CH[3].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[0].u_q/CH[3].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks]
# GT X0Y4
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[1].u_q/CH[0].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[1].u_q/CH[0].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks]
# GT X0Y5
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[1].u_q/CH[1].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[1].u_q/CH[1].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks]
# GT X0Y6
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[1].u_q/CH[2].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[1].u_q/CH[2].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks]
# GT X0Y7
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[1].u_q/CH[3].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[1].u_q/CH[3].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks]
# GT X0Y8
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[2].u_q/CH[0].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[2].u_q/CH[0].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks]
# GT X0Y9
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[2].u_q/CH[1].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[2].u_q/CH[1].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks]
# GT X0Y10
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[2].u_q/CH[2].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[2].u_q/CH[2].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks]
# GT X0Y11
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[2].u_q/CH[3].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[2].u_q/CH[3].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks]
# GT X0Y12
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[3].u_q/CH[0].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[3].u_q/CH[0].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks]
# GT X0Y13
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[3].u_q/CH[1].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[3].u_q/CH[1].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks]
# GT X0Y14
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[3].u_q/CH[2].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[3].u_q/CH[2].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks]
# GT X0Y15
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[3].u_q/CH[3].u_ch/u_gthe4_channel/RXOUTCLK}] -include_generated_clocks]
set_clock_groups -asynchronous -group [get_clocks -of_objects [get_pins {u_ibert_gth_core/inst/QUAD[3].u_q/CH[3].u_ch/u_gthe4_channel/TXOUTCLK}] -include_generated_clocks]


# file: ibert_ultrascale_gth_0.xdc
####################################################################################
##   ____  ____ 
##  /   /\/   /
## /___/  \  /    Vendor: Xilinx
## \   \   \/     Version : 2012.3
##  \   \         Application : IBERT Ultrascale
##  /   /         Filename : example_ibert_ultrascale_gth_0.xdc
## /___/   /\     
## \   \  /  \ 
##  \___\/\___\
##
##
## 
## Generated by Xilinx IBERT 7Series 
##**************************************************************************
##
## Icon Constraints
##
create_clock -name D_CLK -period 10.0 [get_ports gth_sysclkp_i]
set_clock_groups -group [get_clocks D_CLK -include_generated_clocks] -asynchronous
set_property C_CLK_INPUT_FREQ_HZ 100000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER true [get_debug_cores dbg_hub]

##gth_refclk lock constraints
##
set_property PACKAGE_PIN F25 [get_ports gth_refclk0p_i[0]]
set_property PACKAGE_PIN F26 [get_ports gth_refclk0n_i[0]]
set_property PACKAGE_PIN D25 [get_ports gth_refclk1p_i[0]]
set_property PACKAGE_PIN D26 [get_ports gth_refclk1n_i[0]]
set_property PACKAGE_PIN R8 [get_ports gth_refclk0p_i[1]]
set_property PACKAGE_PIN R7 [get_ports gth_refclk0n_i[1]]
set_property PACKAGE_PIN N8 [get_ports gth_refclk1p_i[1]]
set_property PACKAGE_PIN N7 [get_ports gth_refclk1n_i[1]]
set_property PACKAGE_PIN L8 [get_ports gth_refclk0p_i[2]]
set_property PACKAGE_PIN L7 [get_ports gth_refclk0n_i[2]]
set_property PACKAGE_PIN J8 [get_ports gth_refclk1p_i[2]]
set_property PACKAGE_PIN J7 [get_ports gth_refclk1n_i[2]]
set_property PACKAGE_PIN G8 [get_ports gth_refclk0p_i[3]]
set_property PACKAGE_PIN G7 [get_ports gth_refclk0n_i[3]]
set_property PACKAGE_PIN E8 [get_ports gth_refclk1p_i[3]]
set_property PACKAGE_PIN E7 [get_ports gth_refclk1n_i[3]]
##
## Refclk constraints
##
create_clock -name gth_refclk0_1 -period 8.0 [get_ports gth_refclk0p_i[0]]
create_clock -name gth_refclk1_1 -period 8.0 [get_ports gth_refclk1p_i[0]]
set_clock_groups -group [get_clocks gth_refclk0_1 -include_generated_clocks] -asynchronous
set_clock_groups -group [get_clocks gth_refclk1_1 -include_generated_clocks] -asynchronous
create_clock -name gth_refclk0_3 -period 8.0 [get_ports gth_refclk0p_i[1]]
create_clock -name gth_refclk1_3 -period 8.0 [get_ports gth_refclk1p_i[1]]
set_clock_groups -group [get_clocks gth_refclk0_3 -include_generated_clocks] -asynchronous
set_clock_groups -group [get_clocks gth_refclk1_3 -include_generated_clocks] -asynchronous
create_clock -name gth_refclk0_4 -period 8.0 [get_ports gth_refclk0p_i[2]]
create_clock -name gth_refclk1_4 -period 8.0 [get_ports gth_refclk1p_i[2]]
set_clock_groups -group [get_clocks gth_refclk0_4 -include_generated_clocks] -asynchronous
set_clock_groups -group [get_clocks gth_refclk1_4 -include_generated_clocks] -asynchronous
create_clock -name gth_refclk0_5 -period 8.0 [get_ports gth_refclk0p_i[3]]
create_clock -name gth_refclk1_5 -period 8.0 [get_ports gth_refclk1p_i[3]]
set_clock_groups -group [get_clocks gth_refclk0_5 -include_generated_clocks] -asynchronous
set_clock_groups -group [get_clocks gth_refclk1_5 -include_generated_clocks] -asynchronous
##
## System clock pin locs and timing constraints
##
#set_property PACKAGE_PIN AH7 [get_ports gth_sysclkp_i]
#set_property IOSTANDARD DIFF_SSTL15 [get_ports gth_sysclkp_i]


Software Design - Vitis

Note:
  • optional chapter separate

  • sections for different apps

For SDK project creation, follow instructions from:

Vitis

Application

----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2019.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2019.2 xilisf_v5_11

  • Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

zynq_fsbl

TE modified 2019.2 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY

zynq_fsbl_flash

TE modified 2019.2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2019.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
  • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2019.2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

SDK template in ./sw_lib/sw_apps/ available.

zynqmp_fsbl

TE modified 2019.2 FSBL

General:

Module Specific:

zynqmp_fsbl_flash

TE modified 2019.2 FSBL

General:

hello_ibert

Hello TE0808 IBERTis a Xilinx Hello World example as endless loop instead of one console output.

Additional Software

Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:

SI5345

File location <design name>/misc/Si5345/Si5345-*.slabtimeproj

General documentation how you work with these project will be available on Si5345

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


DateDocument Revision

Authors

Description


  • new assembly variants
2020-03-25v.1John Hartfiel
  • initial release

All



Legal Notices