Template Revision 2.12
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
|
<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
width: 100% !important;
max-width: 1200px !important;
}
</style> |
----------------------------------------------------------------------- |
Note for Download Link of the Scroll ignore macro: |
Table of Contents |
Overview
The Trenz Electronic TE0821-01-3BI21FA is a powerful 4 x 5 cm MPSoC module with a Xilinx Zynq UltraScale + ZU3EG. In addition, the module is equipped with a 2 GB DDR4 SDRAM chip, 128 MB flash memory for configuration and data storage, as well as powerful switching power supplies for all required voltages. Robust high-speed connectors provide a large number of inputs and outputs.
This module is pin compatible with Trenz Electronic TE0820 MPSoC modules (JM2 pin 100 is not connected).
The highly integrated modules are smaller than a credit card and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are completely mechanically and largely electrically compatible with each other.
All components cover at least the industrial temperature range from -40 ° C to + 85 ° C. The temperature range in which the module can be used depends on the customer design and the selected cooling. Please contact us for special solutions.
Refer to http://trenz.org/te0821-info for the current online version of this manual and other available documentation.
Key Features
Note: 'description: Important components and connector or other Features of the module → please sort and indicate assembly options Key Features' must be split into 6 main groups for modules and mainboards: - SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
|
- SoC/FPGA
- Xilinx Zynq UltraScale+ XCZU3EG-1SFVC784I
- ZU3EG, 784 Pin Packages
- Application Processor: Quad-Core ARM Cortex-A53 MPCore
- Real-Time Processor: Dual-core ARM Cortex-R5 MPCore
- Graphics Processor: Mali-400 MP2
- RAM/Storage
- 2 GByte DDR4 SDRAM, 32-Bit databus-width
- 128 MByte QSPI boot Flash in dual parallel mode
- 8 GByte e.MMC Memory (up to 64 GByte)
- MAC address serial EEPROM with EUI-48 node identity
- On Board
- Graphic Processing Unit (GPU) :Mali-400 MP2
- Interface
- Power
- All power supplies on board
- Dimension
Block Diagram
Main Components
Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
|
- Xilinx Zynq UltraScale+ XCZU3EG, U1
- Red LED (ERR_OUT), D3
- Green LED (ERR_STATUS), D4
- Red LED (DONE), D1
- 10/100/1000 Mbps energy efficient ethernet transceiver, U8
- 8Gb DDR4, U2-U3
- 512 Mbit QSPI flash memory, U7-U17
- B2B connector Samtec Razor Beam, JM1
- Programmable clock generator, U10
- USB2.0 Transceiver, U18
- B2B connector Samtec Razor Beam, JM3
- B2B connector Samtec Razor Beam, JM2
- 8 GByte eMMC memory, U6
- Lattice Semiconductor MachXO2 System Controller CPLD, U21
Initial Delivery State
Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
Storage device name | Content | Notes |
---|
QSPI Flash Memory | Not programmed |
| eMMC Memory | Not programmed |
| Programmable Clock Generator | Not programmed |
| CPLD (LCMXO2-256HC) | SC0820-02 QSPI Firmware |
|
|
Configuration Signals
- Overview of Boot Mode, Reset, Enables.
|
Two different firmware versions are available, one with the QSPI boot option and other with the SD Card boot option.
MODE Pin | Boot Mode |
---|
Low | QSPI | High | SD Card |
|
Signal | B2B | I/O | Note |
---|
EN | JM1-28 | Input | CPLD Enable Pin |
|
Signals, Interfaces and Pins
Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
|
Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
FPGA Bank | Type | B2B Connector | I/O Signal Count | Voltage Level | Notes |
---|
24 | HD | JM2 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 25 | HD | JM1 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 26 | HD | JM1 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 44 | HD | JM2 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 65 | HP | JM2 | 18x I/O, 9x LVDS Pairs | Variable | Max voltage 1.8V | 65 | HP | JM3 | 16x I/O, 8x LVDS Pairs | Variable | Max voltage 1.8V | 505 | GTR | JM3 | 16x I/O, 8x LVDS Pairs | - | 4x lanes | 505 | GTR CLK | JM3 | 1x Diff Clock | - |
| 501 | MIO | JM1 | 15 I/O | 3.3V |
|
|
JTAG Interface
JTAG access to the Xilinx Zynq UltraScale+ is applicable by using Lattice MachXO CPLD through B2B connector JM2.
JTAG Signal | B2B Connector | Note |
---|
TMS | JM2-93 |
| TDI | JM2-95 |
| TDO | JM2-97 |
| TCK | JM2-99 |
| JTAGEN | JM1-89 | Pulled Low: Xilinx Zynq UltraScale+ MPSoC Pulled High: Lattice MachXO CPLD |
|
MGT Lanes
There are 4x MGT Lanes connected to FPGA Bank 505-GTR.
Lane | Schematic | B2B | Note |
---|
0 | - B505_RX0_P
- B505_RX0_N
- B505_TX0_P
- B505_TX0_N
| |
| 1 | - B505_RX1_P
- B505_RX1_N
- B505_TX1_P
- B505_TX1_N
| |
| 2 | - B505_RX2_P
- B505_RX2_N
- B505_TX2_P
- B505_TX2_N
| |
| 3 | - B505_RX2_P
- B505_RX2_N
- B505_TX2_P
- B505_TX2_N
| |
|
|
MIO Pins
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin | Connected to | B2B | Notes |
---|
MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
|
MIO Pin | Connected to | B2B | Notes |
---|
0...5 | QSPI Flash, U7 | - | SPI Flash | 7...12 | QSPI Flash, U17 | - | SPI Flash | 13...23 | eMMC, U6 |
|
| 24 | ETH Transceiver, U8 | - | ETH_RST | 25 | USB2.0 Transceiver, U18 | - | OTG_RST | 26...33 | User MIO | JM1 |
| 34...37 | N.C | - | N.C | 38...39 | EEPROM, U25 | - | I2C_SDA/SCL | 40...45 | N.C |
| N.C | 46...51 | SD Card | JM1 |
| 52...63 | USB2.0 Transceiver, U18 | - |
| 63...77 | Ethernet Transceiver, U8 | - |
|
|
Test Points
you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point | Signal | B2B | Notes |
---|
10 | PWR_PL_OK | J2-120 |
|
|
Test Point | Signal | Connected to | Notes |
---|
1 | I2C_SCL | EEPROM, U25 |
| 2 | I2C_SDA | EEPROM, U25 |
| 3 | SRST_B | FPGA Bank 503 | PSCONFIG | 4 | PS_CLK | FPGA Bank 503 | PSCONFIG | 5 | PROG_B | FPGA Bank 503 | PSCONFIG | 6 | INIT_B | FPGA Bank 503 | PSCONFIG | 7 | DONE | Red LED, D1 |
| 8 | PS_LP0V85 | Voltage Regulator, U12 |
| 9 | DDR_2V5 | Voltage Regulator, U4 |
| 10 | PS_AVCC | Voltage Regulator, U9 |
| 11 | DDR_1V2 | Voltage Regulator, U15 |
| 12 | PS_AVTT | Voltage Regulator, U3 |
| 13 | PS_FP0V85 | Voltage Regulator, U26 |
| 14 | POR_B | Voltage Translator, U19 |
| 15 | PS_PLL | Voltage Regulator, U23 |
| 16 | PL_VCCINT | Voltage Regulator, U5 |
|
|
On-board Peripherals
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
|
Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
Chip/Interface | Designator | Notes |
---|
QSPI Flash | U7, U17 |
| EEPROM | U25 |
| DDR4 SDRAM | U2,U3 |
| Oscillators | U32, U14, U12 |
| CPLD | U21 |
| LEDs | D1...3 |
|
|
Quad SPI Flash Memory
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
MIO Pin | Schematic | U?? Pin | Notes |
---|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
EEPROM
MIO Pin | Schematic | U25 Pin | Notes |
---|
MIO39 | I2C_SDA | SDA |
| MIO38 | I2C_SCL | SCL |
|
|
MIO Pin | I2C Address | Designator | Notes |
---|
MIO38...39 | 0x50 | U25 |
|
|
LEDs
Designator | Color | Connected to | Active Level | Note |
---|
D1 | Red | DONE | High |
| D2 | Green | ERR_STATUS | High |
| D3 | Red | ERR_OUT | High |
|
|
DDR3 SDRAM
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE0821 SoM has 8 Gb volatile DDR4 SDRAM IC for storing user application code and data.
- Part number: K4A8G165WB-BIRC
- Supply voltage: 1.2V
- Speed: 2400 mbps
- Temperature: -40 ~ 95 °C
Ethernet
U?? Pin | Signal Name | Connected to | Signal Description | Note |
---|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Clock Sources
Designator | Description | Frequency | Note |
---|
U11 | MEMS Oscillator | 25 MHz |
| U14 | MEMS Oscillator | 25 MHz |
|
|
Programmable Clock Generator
There is a programmable clock generator on-board (U??) provided in order to generate variable clocks for the module. Programming can be done using I2C via PIN header J??. The I2C Address is 0x??.
U?? Pin
| Signal | Connected to | Direction | Note |
---|
IN0 |
|
|
|
| IN1 |
|
|
|
| IN2 |
|
|
|
| IN3 |
|
|
|
| XAXB |
|
|
|
| SCLK |
|
|
|
| SDA |
|
|
|
| OUT0 |
|
|
|
| OUT1 |
|
|
|
| OUT2 |
|
|
|
| OUT3 |
|
|
|
| OUT4 |
|
|
|
| OUT5 |
|
|
|
| OUT6 |
|
|
|
| OUT7 |
|
|
|
| OUT8/OUT9 |
|
|
|
|
|
Power and Power-On Sequence
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
|
Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
Power Consumption
Power Input Pin | Typical Current |
---|
VIN | TBD* |
|
* TBD - To Be Determined
Power Distribution Dependencies
Power-On Sequence
Voltage Monitor Circuit
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
|
Power Rails
Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
---|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Bank Voltages
Board to Board Connectors
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
|
Technical Specifications
Absolute Maximum Ratings
Symbols | Description | Min | Max | Unit |
---|
|
|
|
| V |
|
|
|
| V |
|
|
|
|
|
|
|
|
|
|
|
Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
---|
|
|
| V | See ???? datasheets. |
|
|
| V | See Xilinx ???? datasheet. |
|
|
| °C | See Xilinx ???? datasheet. |
|
|
| °C | See Xilinx ???? datasheet. |
|
Physical Dimensions
PCB thickness: 1.74 mm.
Currently Offered Variants
Revision History
Hardware Revision History
Date | Revision | Changes | Documentation Link |
---|
2019-04-26 | REV01 | | REV01 |
|
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
|
Date | Revision | Contributor | Description |
---|
| | | | -- | all | | |
|
Disclaimer