The reference architecture can be tested in two ways:
To test the USB communication in the Reference Architecture case is necessary
To completely test the Reference Architecture is necessary
The procedures are the following.
Procedure SDK: opening and update SDK project only Compile and link time less than 1 minute. | Procedure XPS+SDK: opening and update both XPS and SDK projects Resynthesis of reference HW could take from 10 minutes to 1 hour(1) |
---|---|
Update XPS project from an old version to a new one | |
Open SDK project and (if needed) update the SDK project from an old version to a new one | Recreate SDK project using the new exported HW project |
Generate a new link script | |
Download the bitstream to the FPGA | |
Check the fiirmware of FX2 microcontroler | |
Run the demo project | |
USB communication tests + DMA tests |
(1) It depends on which computer is used (workstation, regular PC or low-end PC).
For old version of Xilinx EDK with older version of Project Reference (they do no longer exist on GitHub) the procedure is the folowing
To use the "demo" application contained in TE0xxx-Reference-Designs\reference-TE0xxx\SDK\SDK_Workspace, you should (1) copy GitHub's "TE-EDK-IP" folder (from https://github.com/Trenz-Electronic/TE-EDK-IP) to the folder that contains the folder "reference-TE0xxx":
otherwise you must copy the contents of GitHub's 'TE-EDK-IP' folder inside the already existent empty folder "TE0xxx-Reference-Designs\TE-EDK-IP".
You should not alter folder nesting because is a Xilinx Platform Studio requirements
The FX2 microcontroller on the TE USB FX2 module should contain valid firmware before proceeding.
To use the demo project without the XMD UART, you need to use "RS232" instead of "debug_module" as standard in/out port. Otherwise the application running on the Microblaze processor freezes if you disconnect the XMD. To accomplish that you need to set up the Microblaze "Software Platform Settings".
The UART is then redirected to external pins, which are defined in the data/system.ucf file. The following snippet shows the case of the TE0300 series modules:
Module RS232 constraints*
Net fpga_0_RS232_RX_pin LOC=B13;
Net fpga_0_RS232_TX_pin LOC=B14;
Please refer to the table below for other module series relevant to this application note.
TE series | RS232_RX | RS232_RX | RS232_TX | RS232_TX |
---|---|---|---|---|
TE0300 | R6 | J5-29 | P6 | J5-31 |
TE0320 | V17 | J5-IO18 | W17 | J5-IO19 |
TE0630 | Y7 | J5-29 | AB7 | J5-31 |
TE0304 | It doesn't apply | J1-3 | It doesn't apply | J1-2 |
TE0323 | It doesn't apply | J4-35 | It doesn't apply | J4-37 |
host (PC) | TX | TX | RX | RX |
Sample UART to USB virtual COM port converter.
Sample UART to USB virtual COM port converter: signal detail.