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Overview
CPLD Device with designator U46: 10M08SAU169
Feature Summary
- something to have access to CPLD to read out status of Power management
- Power management
- Reset
Firmware Revision and supported PCB Revision
See Document Change History
Product Specification
Port Description
Name / opt. VHD Name | Direction | Pin | Pullup/Down | Bank Power | Description |
---|---|---|---|---|---|
JTAGEN | in | E5 | -- | 3.3V | fixed to 3.3V |
TCK_MAX10 | in | G2 | -- | 3.3V | JTAG |
TMS_MAX10 | in | G1 | -- | 3.3V | JTAG |
TDO_MAX10 | out | F6 | -- | 3.3V | JTAG |
TDI_MAX10 | in | F5 | -- | 3.3V | JTAG |
EN_VTT_PL_DDR | out | J2 | 3.3V LVCMOS |
| |
EN_2V5_PL_DDR | out | J1 | 3.3V LVCMOS |
| |
EN_1V2_PL_DDR | out | H4 | 3.3V LVCMOS |
| |
PG_1V2_PL_DDR | in | H5 | weak pull-up | 3.3V LVCMOS |
|
EN_1V8_PS_AUX | out | M2 | 3.3V LVCMOS |
| |
PG_SOM | out | M1 | weak pull-up | 3.3V LVCMOS |
|
PG_VCCINT | in | N3 | weak pull-up | 3.3V LVCMOS |
|
LTM_FAULT | in | N2 | 3.3V LVCMOS |
| |
SC_EXT_2 | out | L3 | 3.3V LVCMOS |
| |
M_SDA | inout | M3 | 3.3V LVCMOS |
| |
MR | out | K2 | 3.3V LVCMOS |
| |
EN_SOM | in | K1 | weak pull-up | 3.3V LVCMOS |
|
SC_EXT_3 | in | L2 | 3.3V LVCMOS |
| |
SMB_ALERTn | in | L4 | 3.3V LVCMOS |
| |
PG_2V5_PL_DDR | in | L5 | weak pull-up | 3.3V LVCMOS |
|
EN_LTM_RUNP | out | M5 | 3.3V LVCMOS |
| |
M_SCL | inout | M4 | 3.3V LVCMOS |
| |
nRST_SYS | out | K5 | 3.3V LVCMOS |
| |
EN_0V9_GTH_AVCC | out | N5 | 3.3V LVCMOS |
| |
EN_0V9_GTY_AVCC | out | N4 | 3.3V LVCMOS |
| |
PG_1V2_PS_DDR | in | M7 | weak pull-up | 3.3V LVCMOS |
|
PG_0V9_GTH_AVCC | in | N6 | weak pull-up | 3.3V LVCMOS |
|
PG_0V9_GTY_AVCC | in | N8 | weak pull-up | 3.3V LVCMOS |
|
EN_3V3_SW | out | N7 | 3.3V LVCMOS |
| |
EN_1V2_PS_PLL | out | J6 | 3.3V LVCMOS |
| |
PG_1V8_PS_GTR_AVTT | in | M9 | weak pull-up | 3.3V LVCMOS |
|
PG_1V8 | in | M8 | weak pull-up | 3.3V LVCMOS |
|
EN_2V5_PS_DDR | out | M13 | 3.3V LVCMOS |
| |
PG_1V2_GTY_AVTT | in | N9 | weak pull-up | 3.3V LVCMOS |
|
EN_1V2_GTY_AVTT | out | N10 | 3.3V LVCMOS |
| |
M_INT | L11 | 3.3V LVCMOS | |||
EN_1V8_VCC_ADC | out | M11 | 3.3V LVCMOS |
| |
PG_0V85_PS_GTR_AVCC | in | K8 | weak pull-up | 3.3V LVCMOS |
|
EN_VTT_PS_DDR | out | J8 | 3.3V LVCMOS |
| |
EN_1V8 | out | L10 | 3.3V LVCMOS |
| |
EN_1V8_GTY_AUX | out | M10 | 3.3V LVCMOS |
| |
PG_2V3 | in | N12 | weak pull-up | 3.3V LVCMOS |
|
| |||||
EN_1V8_GTR_AVTT_PS | out | K10 | 3.3V LVCMOS |
| |
EN_1V8_GTH_AUX | out | K11 | 3.3V LVCMOS |
| |
EN_1V8_AUX | out | K12 | 3.3V LVCMOS |
| |
EN_1V2_GTH_AVTT | out | J12 | 3.3V LVCMOS |
| |
PG_3V3_SW | in | J9 | weak pull-up | 3.3V LVCMOS |
|
EN_1V2_PS_DDR | out | J13 | 3.3V LVCMOS |
| |
EN_0V85_GTR_AVCC_PS | out | H13 | 3.3V LVCMOS |
| |
PG_1V2_GTH_AVTT | in | H9 | weak pull-up | 3.3V LVCMOS |
|
EN_VCCINT | out | H8 | 3.3V LVCMOS |
| |
EN_2V3 | out | G13 | 3.3V LVCMOS |
| |
PG_1V8_AUX | in | G12 | weak pull-up | 3.3V LVCMOS |
|
PG_2V5_PS_DDR | in | L13 | weak pull-up | 3.3V LVCMOS |
|
Functional Description
Power
All power regulators are controlled by the power sequencer core. It enables and discharges the power regulators and monitors the power good signals.
The power-up sequence corresponds to AMD's recommendations and is shown in the table below:
Power Group | Power enable signal (CPLD output signal) | Power good signal (CPLD input signal) | Notes |
---|---|---|---|
0 | EN_VCCINT | PG_VCCINT | -- |
EN_2V3 | PG_2V3 | -- | |
EN_3V3_SW | PG_3V3_SW | +3.3V_SW output signal from U52 | |
1 | EN_1V8 | PG_1V8 | -- |
EN_1V8_AUX | PG_1V8_AUX | -- | |
EN_1V8_PS_AUX | -- | -- | |
EN_1V2_PS_PLL | -- | -- | |
EN_0V9_GTH_AVCC | PG_0V9_GTH_AVCC | -- | |
EN_0V9_GTY_AVCC | PG_0V9_GTY_AVCC | -- | |
EN_1V8_VCC_ADC | -- | -- | |
2 | EN_1V2_PS_DDR | PG_1V2_PS_DDR | -- |
EN_1V2_PL_DDR | PG_1V2_PL_DDR | -- | |
EN_1V2_GTH_AVTT | PG_1V2_GTH_AVTT | -- | |
EN_1V2_GTY_AVTT | PG_1V2_GTY_AVTT | -- | |
3
| EN_VTT_PS_DDR | -- | -- |
EN_0V85_PS_GTR_AVCC | PG_0V85_PS_GTR_AVCC | -- | |
EN_VTT_PL_DDR | -- | -- | |
EN_2V5_PL_DDR | PG_2V5_PL_DDR | -- | |
EN_2V5_PS_DDR | PG_2V5_PS_DDR | -- | |
EN_1V8_GTH_AUX | -- | -- | |
EN_1V8_GTY_AUX | -- | -- | |
4 | EN_1V8_PS_GTR_AVTT | PG_1V8_PS_GTR_AVTT | -- |
Power Group | Power enable signal (CPLD output signal) | Power good signal (CPLD input signal) | Notes |
---|---|---|---|
0 | -- | EN_SOM |
|
1 | EN_VCCINT | PG_VCCINT | -- |
EN_2V3 | PG_2V3 | -- | |
EN_3V3_SW | PG_3V3_SW | +3.3V_SW output signal from U52 | |
2 | EN_1V8 | PG_1V8 | -- |
EN_1V8_AUX | PG_1V8_AUX | -- | |
EN_1V8_PS_AUX | -- | -- | |
EN_1V2_PS_PLL | -- | -- | |
EN_0V9_GTH_AVCC | PG_0V9_GTH_AVCC | -- | |
EN_0V9_GTY_AVCC | PG_0V9_GTY_AVCC | -- | |
EN_1V8_VCC_ADC | -- | -- | |
3 | EN_1V2_PS_DDR | PG_1V2_PS_DDR | -- |
EN_1V2_PL_DDR | PG_1V2_PL_DDR | -- | |
EN_1V2_GTH_AVTT | PG_1V2_GTH_AVTT | -- | |
EN_1V2_GTY_AVTT | PG_1V2_GTY_AVTT | -- | |
4
| EN_VTT_PS_DDR | -- | -- |
EN_0V85_PS_GTR_AVCC | PG_0V85_PS_GTR_AVCC | -- | |
EN_VTT_PL_DDR | -- | -- | |
EN_2V5_PL_DDR | PG_2V5_PL_DDR | -- | |
EN_2V5_PS_DDR | PG_2V5_PS_DDR | -- | |
EN_1V8_GTH_AUX | -- | -- | |
EN_1V8_GTY_AUX | -- | -- | |
5 | EN_1V8_PS_GTR_AVTT | PG_1V8_PS_GTR_AVTT | -- |
6 | PG_SOM | -- | -- |
JTAG UART
As the power sequencer monitors all voltages and there is no visual feedback in the event of an error, the JTAG UART was implemented.
The command "nios2-terminal.exe" in the NIOS II command shell is used to output the power good signals and the revision of the CPLD firmware and the PCB.
see also https://www.intel.com/content/www/us/en/docs/programmable/683130/21-4/jtag-uart-core.html
I2C interface
CPLD firmware consists of an I2C Slave to Avalon-MM Master Bridge Intel FPGA IP i2c t GPIO block. This subsystem provides i2c protocol interface to 32-bit (4 x 8-bit) (GPIO_input[31:0]) registers for reading from CPLD and (4 x 8-bit) (GPIO_output[31:0]) registers for writing in CPLD as general purpose parallel input and output (I/Os). The written and read data is communicated from/to FPGA via i2c bus interface protocol. The address of this block in the firmware is 0x20. In this case related i2c bus is bus 1.
Register | Direction in CPLD | Address |
---|---|---|
GPIO_input[7:0] | Output (reading from CPLD) | 0x00 |
GPIO_input[15:8] | Output (reading from CPLD) | 0x01 |
GPIO_input[23:16] | Output (reading from CPLD) | 0x02 |
GPIO_input[31:24] | Output (reading from CPLD) | 0x03 |
GPIO_output[7:0] | Input (writing to CPLD) | 0x00 |
GPIO_output[15:8] | Input (writing to CPLD) | 0x01 |
GPIO_output[23:16] | Input (writing to CPLD) | 0x02 |
GPIO_output[31:24] | Input (writing to CPLD) | 0x03 |
NOSEQ pin
This pin in PCB REV04 with old CPLD firmware version (REV04) is used as boot mode pin select. If CPLD is programmed with SC0820_qspi_sd_jtag.jed as jed file and NOSEQ is high, JTAG boot mode will be selected. For PCB REV05 or PCB REV04 with new CPLD firmware (CPLD firmware REV05) NOSEQ pin can be used by user as GPIO pin and accessed via i2c interface. In this case the following table can be used:
NOSEQ pin as output | Condition | Command in linux console |
---|---|---|
'1' | GPIO_output(16) = '1' | i2cset -y 1 0x20 0x02 0x01 |
'0' | GPIO_output(16) = '0' | i2cset -y 1 0x20 0x02 0x00 |
NOSEQ pin as input | Description | Command in linux console |
Reading state of NOSEQ pin | GPIO_input(16) = NOSEQ | i2cget -y 1 0x20 0x02 |
Access to CPLD Registers
CPLD registers can be accessed via i2c interface. In the following table is shown how these registers can be read or written:
Register Address | Direction in CPLD | Related instruction in linux console to access the register |
---|---|---|
0x00 | Output (reading from CPLD) | i2cget -y 1 0x20 0x00 |
0x01 | Output (reading from CPLD) | i2cget -y 1 0x20 0x01 |
0x0C | Input (writing to CPLD) | i2cset -y 1 0x20 0x00 <data> |
GPIO_output[15:8] | Input (writing to CPLD) | i2cset -y 1 0x20 0x01 <data> |
GPIO_output[23:16] | Input (writing to CPLD) | i2cset -y 1 0x20 0x02 <data> |
GPIO_output[31:24] | Input (writing to CPLD) | i2cset -y 1 0x20 0x03 <data> |
Some of these registers are using to show some information same as CPLD revision and boot mode while booting.
Register | Address | related data | Read/write by user | Description |
---|---|---|---|---|
GPIO_input[7:0] | 0x00 | CPLD REVISION (8 bits) | No | |
GPIO_input[15:8] | 0x01 | "00" & BOOTMODE_GEN (2 bits) & PUDC (1 bit) & CPLD_BM (1 bit) & BOOT_MODE (2 bits) | No | BOOTMODE_GEN is a generic parameter in firmware code to select type of jed-file. For example if this parameter is 3 , then by programming the related jed-file the user can have all boot mode options. (QSPI/JTAG/SD Card/eMMC). PUDC is the state of PUDC pin of FPGA. CPLD_BM is a parameter to show if boot mode selection is executed via hardware ( if low) or software (if high) BOOT_MODE shows selected boot mode. |
GPIO_input8[16] | 0x02 | NOSEQ pin | Yes | |
Register | Address | related data | Description | |
GPIO_output[16] | 0x02 | NOSEQ pin | Yes |
If CPLD firmware version is REV05, then boot mode, CPLD revision and some features of the board will be displayed in the linux console via FSBL code while booting. The format of these informations are shown in the following:
Information | Displayed in Linux console | Description |
---|---|---|
CPLD Revision | CPLD_REV = <cpld revision> | |
Boot mode selection procedure | CPLD_BM = < bm selection procedure> |
|
Jed file that on CPLD is programmed | BOOTMODE_GEN = < jed file type> |
|
PUDC pin state | PUDC_MODE = <pudc state> |
|
Boot mode | BOOT_MODE = <boot mode> |
|
The CPLD revision, boot mode and other informations will be displayed while booting as shown:
If PCB revision is REV04 and CPLD firmware version is older than REV05 (for example REV04) , then it will not be displayed these informations same as boot mode while booting and the following message will be displayed:
Appx. A: Change History
For PCB REV01 and REV02 Documentation available on: TE0820-REV01_REV02 CPLD
Revision Changes
- REV02 to REV03
- changed top design from block design to text design
- REV01 to REV02
- added Pin L3 SC_EXT_2 as output and set to VCC to enable USB
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
---|---|---|---|---|---|
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Appx. B: Legal Notices
Data Privacy
Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy
Document Warranty
The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.
Limitation of Liability
In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.
Copyright Notice
No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.
Technology Licenses
The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.
Environmental Protection
To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.
REACH, RoHS and WEEE
REACH
Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).
RoHS
Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.
WEEE
Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).
Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.
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