PCN-20250819 TEF0008-02 to TEF0008-03 Hardware Revision Change

Products Affected

This change affects all Trenz Electronic TEF0008 boards: TEF0008-02-D.

Changes

#1 Changed DCDC EP53A7HQI (U6) to MPM3834CGPA-Z and adapted power circuit.

Type: Schematic Change

Reason: EOL of Component.

Impact: None. Minor changes in electrical characteristics.

#2 Connected DCDC (U6) power good signal "PG_1V8" via added resistor (R49) to FMC power good signal "PG_M2C".

Type: Schematic Change

Reason: Improve power-sequence handling.

Impact: Signal "PG_M2C" is asserted only after power rail "1.8V" powered-up.

#3 Changed EEPROM (U4) 24LC128-I/ST to M24C32-RDW6TP.

Type: BOM Change

Reason: Follow VITA 57.1 standard.

Impact: Decreased memory size from 128 kbit to 32 kbit.

#4 Changed EEPROM (U4) I2C address.

• Default assembly option:
  • Connected FMC GA0 to EERPOM address bit 1 via resistor (R40 (default: assembled)).
  • Connected FMC GA1 to EEPROM address bit 0 via resistor (R39 (default: assembled)).
• Backwards compatible assembly option (on request):
  • Connected FMC GA0 to EEPROM address bit 0 via resistor (R38 (default: not assembled)).
  • Connected FMC GA1 to EEPROM address bit 1 via resistor (R41 (default: not assembled)).

Type: Schematic Change

Reason: Follow VITA 57.1 standard.

Impact: Changed I2C address needs to be considered within system design.

#5 Added second differential clock at system controller (U5).

• Connected net "GCLKF_P/N" between PLL (U2) pin 28 and 27 and system controller (U5) pin H4 and H5.
• Connected 0.9 V reference voltage net "0V9_VTT" at system controller (U5) pin L1.
• Supplied PLL (U2) pin 26 with "PLL_VDD_1V8" and added decoupling capacitor C61.
• Added clock termination circuit (R43 ... R47, C62, C63).
• Updated clock documentation.

Type: Schematic Change

Reason: Add differential clock and obtain already existing clock at the same time.

Impact: None. Already existing clock at system controller (U5) pin H6 and G5 can be used as before and a new differential clock should be available now.

#6 Added DIP switch (S1) to control signal "JTAG_EN" and add a user DIP switch together with pull-up resistor (R48).

Type: Schematic Change

Reason: Enable signal "JTAG_EN" control.

Impact: None. Enable possibility to disable system controller JTAG interface.

#7 Changed commercial grade system controller 10M08SAU169C7G (U5) to industrial grade system controller 10M08SAU169I7G.

Type: BOM Change

Reason: Increase temperature range.

Impact: None. Increase temperature range.

#8 Changed 10 µF, 10 V capacitor (C35, C38, C41, C44, C47, C50, C53, C56) to 22 µF, 6.3 V.

Type: BOM Change

Reason: Follow SFP+ recommendation.

Impact: None. Minor changes in electrical characteristics.

#9 Changed 1 µH inductor (L4 ... L11) to 4.7 µH.

Type: Schematic Change

Reason: Follow SFP+ recommendation.

Impact: None. Minor changes in electrical characteristics.

#10 Removed track-it traceability pad (S/N1) from PCB completely.

Type: Schematic Change

Reason: EOL of Component.

Impact: None.

#11 Added test points (TP11, TP12).

Type: Schematic Change

Reason: Improve measurement possibilities.

Impact: None.

#12 Added UKCA-, RoHS- and ESD-logo.

Type: PCB Change

Reason: Improve product classification.

Impact: None.

Method of Identification

The model code and revision number (TEF0008-03) are printed on the bottom side of the PCB.

Production Shipment Schedule

From February 2026, after old stock is gone. If the new revision is not suitable for your application and still the former revision of the board is needed, please contact us.

This PCN follows JEDEC Standard J-STD-046.