JTAG and UART connections are available through Micro USB connector. External JTAG Programmer is not needed.
Pin name
Connected to
Direction
Note
BDBUS0
E18
in
uart rx
BDBUS1
F16
out
uart tx
UART
Push Buttons
Reset Button: reset Cyclone V (connected to nCONFIG Pin)
User Button: connected to FPGA Pin L17
LEDs
There are 2 status LEDs and 8 user LEDs which can be used for variant purposes.
Name
Color
Connected to
Active Level
Note
Power LED
Green
3.3V
low
3.3V status LED
CONF_DONE
Red
CONF_DONE pin
high
--
LED1
Red
P4
high
--
LED2
Red
M4
high
--
LED3
Red
M3
high
--
LED4
Red
N3
high
--
LED5
Red
V2
high
--
LED6
Red
L2
high
--
LED7
Red
L1
high
--
LED8
Red
K1
high
--
Module LEDs
CRUVI Pin Header J3
The Pin Header J3 is based on CRUVI Standard. For more information, please visit www.cruvi.com.
The Pins of the pin header J3 are connected to the FPGA Bank 7A and 8A. With the VSEL pin the voltage of these banks must be selected between 1.8V and 3.3V (depends on connected periphery):