This section describes how the various pins on B2B connectors JM4 and JM5 connect with TE0320 on-board components. In this chapter, most of naming conventions and colour coding scheme are taken from the official Xilinx Spartan-3A DSP documentation.
The pin label is abbreviated but descriptive for each pin. All I/O pins begin with IO. If a pin can be used as a differential signal, the name includes an _Lxxy_b suffix, where
Dual- or multi-purpose pins have a name composed of the signal names referring to each possible pin function (e. g. IO_L52P_2 / D0 / DIN / MISO). _B is used as the active-Low designator, as in CSI_B.
A differential clock input requires two global clock inputs. The P and N inputs follow the same configuration as for standard inputs on those pins. The clock inputs that get paired together are consecutive pins in clock number, an even clock number and the next higher odd value. For example, GCLK0 and GCLK1 are a differential pair.
Most pins of B2B connectors JM4 and JM5 are general-purpose, user-defined I/O pins (GPIOs). There are, however, up to 9 different functional types of pins on the TE0320, as outlined in Table 39. In pin-out tables 40 and 41, the individual pins are colour-coded according to pin type as in Table 39.
type | description |
I/O | Unrestricted, general-purpose user-I/O pin. Most pins can be paired together to form differential I/Os. |
Dual-purpose pin used in some configuration modes during the configuration process and then usually available as a user I/O after configuration. If the pin is not used during configuration, this pin behaves as an I/O-type pin. See Xilinx UG332: Spartan-3 Generation Configuration User Guide for additional information on these signals. | |
| VREF0 provides a reference voltage input for certain I/O standards. See paragraph 6.9 Voltage Reference VREF0 for additional information on this signal. |
| Either a user-I/O pin or an input to a specific clock buffer driver. Packages have 16 global clock inputs that optionally clock the entire device. See the Using Global Clock Resources chapter in UG331: Spartan-3 Generation FPGA User Guide for additional information on these signals. |
| Dedicated configuration pin, two per device. Not available as a user-I/O pin. Every package has two dedicated configuration pins. These pins are powered by VCCAUX. See Xilinx UG332: Spartan-3 Generation Configuration User Guide for additional information on these signals. |
| Control and status pins for the power-saving Suspend mode. SUSPEND is a dedicated pin and is powered by VCCAUX. AWAKE is a Dual-Purpose pin. Unless Suspend mode is enabled in the application, AWAKE is available as a user-I/O pin. |
Dedicated JTAG pin - 4 per device. Not available as a user-I/O pin. Every package has four dedicated JTAG pins. These pins are powered by VCCAUX. | |
Dedicated ground pin. All must be connected. | |
TE | Trenz Electronic specific pin type. See the description of each pin in the user manual for additional information on the corresponding signals. |
Table 39: types of pins on TE0320.
sup ply | bank | type | FPGA pin | FPGA ball | JM4 singal | JM4 | pin | JM4 singal | FPGA ball | FPGA pin | type | bank | sup ply |
3.3 V | - | out | - | - | 3.3V | 1 | 2 | GND | - | - | GND | GND | GND |
VcccIO0 | 0 | I/O | IO_L20P_0 | F15 | JM4-IO01 | 3 | 4 | B2B_D_P | - | - | I/O | - | USB |
VcccIO0 | 0 | I/O | IO_L21N_0 | C16 | JM4-IO02 | 5 | 6 | B2B_D_N | - | - | I/O | - | USB |
GND | GND | GND | - | - | GND | 7 | 8 | JM4-IO34 | K12 | IO_L39N_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O | IO_L21P_0 | D17 | JM4-IO03 | 9 | 10 | JM4-IO35 | J12 | IO_L39P_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O | IO_L22N_0 | C15 | JM4-IO04 | 11 | 12 | JM4-IO36 | D8 | IO_L40N_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O | IO_L22P_0 | D16 | JM4-IO05 | 13 | 14 | JM4-IO37 | C8 | IO_L40P_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O | IO_L23N_0 | A15 | JM4-IO06 | 15 | 16 | GND | - | - | GND | GND | GND |
VcccIO0 | 0 | I/O | IO_L23P_0 | B15 | JM4-IO07 | 17 | 18 | JM4-IO38 | C6 | IO_L41N_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O | IO_L24N_0 | F14 | JM4-IO08 | 19 | 20 | JM4-IO39 | B6 | IO_L41P_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O | IO_L24P_0 | E14 | JM4-IO09 | 21 | 22 | JM4-IO40 | C7 | IO_L42N_0 | I/O | 0 | VcccIO0 |
GND | GND | GND | - | - | GND | 23 | 24 | JM4-IO41 | B7 | IO_L42P_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O GCLK | IO_L25N_0 GCLK5 | J14 | JM4-IO10 | 25 | 26 | JM4-IO42 | K11 | IO_L43N_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O GCLK | IO_L25P_0 GCLK4 | K14 | JM4-IO11 | 27 | 28 | JM4-IO43 | J11 | IO_L43P_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O GCLK | IO_L26N_0 GCLK7 | A14 | JM4-IO12 | 29 | 30 | VcccIO0 | - | - | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O GCLK | IO_L26P_0 GCLK6 | B14 | JM4-IO13 | 31 | 32 | JM4-IO44 | D6 | IO_L44N_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O GCLK | IO_L27N_0 GCLK9 | G13 | JM4-IO14 | 33 | 34 | JM4-IO45 | C5 | IO_L44P_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O GCLK | IO_L27P_0 GCLK8 | F13 | JM4-IO15 | 35 | 36 | JM4-IO46 | B4 | IO_L45N_0 | I/O | 0 | VcccIO0 |
VREF | 0 | in | - | - | VREF0 | 37 | 38 | JM4-IO47 | A4 | IO_L45P_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O GCLK | IO_L28N_0 GCLK11 | C13 | JM4-IO16 | 39 | 40 | JM4-IO48 | H10 | IO_L46N_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O GCLK | IO_L28P_0 GCLK10 | B13 | JM4-IO17 | 41 | 42 | JM4-IO49 | G10 | IO_L46P_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O | IO_L29N_0 | B12 | JM4-IO18 | 43 | 44 | VcccIO0 | - | - | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O | IO_L29P_0 | A12 | JM4-IO19 | 45 | 46 | JM4-IO50 | H9 | IO_L47N_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O | IO_L30N_0 | C12 | JM4-IO20 | 47 | 48 | JM4-IO51 | G9 | IO_L47P_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O | IO_L30P_0 | D13 | JM4-IO21 | 49 | 50 | JM4-IO52 | E7 | IO_L48N_0 | I/O | 0 | VcccIO0 |
GND | GND | GND | - | - | GND | 51 | 52 | JM4-IO53 | F7 | IO_L48P_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O | IO_L33N_0 | B10 | JM4-IO22 | 53 | 54 | JM4-IO54 | B3 | IO_L51N_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O | IO_L33P_0 | A10 | JM4-IO23 | 55 | 56 | JM4-IO55 | A3 | IO_L51P_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O | IO_L34N_0 | D10 | JM4-IO24 | 57 | 58 | GND | - | - | GND | GND | GND |
VcccIO0 | 0 | I/O | IO_L34P_0 | C10 | JM4-IO25 | 59 | 60 | JM4-IO56 | C23 | IO_L06N_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O | IO_L35N_0 | H12 | JM4-IO26 | 61 | 62 | JM4-IO57 | D23 | IO_L06P_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O | IO_L35P_0 | G12 | JM4-IO27 | 63 | 64 | JM4-IO58 | A22 | IO_L07N_0 | I/O | 0 | VcccIO0 |
GND | GND | GND | - | - | GND | 65 | 66 | JM4-IO59 | B23 | IO_L07P_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O | IO_L36N_0 | B9 | JM4-IO28 | 67 | 68 | JM4-IO60 | G17 | IO_L08N_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O | IO_L36P_0 | A9 | JM4-IO29 | 69 | 70 | JM4-IO61 | H17 | IO_L08P_0 | I/O | 0 | VcccIO0 |
VcccIO0 | 0 | I/O | IO_L37N_0 | D9 | JM4-IO30 | 71 | 72 | VccAux | - | - | out | VccAux | VccAux |
VcccIO0 | 0 | I/O | IO_L37P_0 | E10 | JM4-IO31 | 73 | 74 | TDI | G7 | TDI | JTAG | VccAux | VccAux |
VcccIO0 | 0 | I/O | IO_L38N_0 | B8 | JM4-IO32 | 75 | 76 | TDO | E23 | TDO | JTAG | VccAux | VccAux |
VcccIO0 | 0 | I/O | IO_L38P_0 | A8 | JM4-IO33 | 77 | 78 | TCK | D4 | TCK | JTAG | VccAux | VccAux |
GND | GND | GND | - | - | GND | 79 | 80 | TMS | A25 | TMS | JTAG | VccAux | VccAux |
Traces of differential signals pairs are :
For applications where traces length has to be matched or timing differences have to be compensated, Table 42 and Table 43 list the trace length of I/O signal lines measured from FPGA balls to B2B connector pins.
Pairs of pins that form a differential I/O pair appear colored together in the table. An electronic version of these pin-out tables are available for download from the Trenz Electronic support area of the web site.