Table of Contents
Overview
The Trenz Electronic TE0782 is a high-performance, industrial-grade SoM (System on Module) with industrial temperature range based on Xilinx Zynq-7000 SoC. It is equipped with a Xilinx Zynq-7 (XC7Z035, XC7Z045 or XC7Z100).
These highly integrated modules with an economical price-performance-ratio have a form-factor of 8,5 x 8,5 cm and are available in several versions.
All parts cover at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Contact us for modified PCB-equipping due increasing cost-performance-ratio and prices for large-scale order.
This SoM has following peripherals on board:
- 2 x Gbps Ethernet PHY transceiver
- 2 x 512 MByte DDR3 SDRAM
- 32 MByte QSPI Flash Memory for configuration, operation and to store data
- eMMC (4 GByte in standard configuration)
- 2 x USB PHY transceiver
- 16 GTX high-performance transceiver lanes
- powerful switch-mode power supplies for all on-board voltages
- large number of configurable I/Os is provided via rugged high-speed stacking strips
Key Features
- Xilinx Zynq-7 XC7Z035, XC7Z045 or XC7Z100 SoM
- Rugged for shock and high vibration
- Dual ARM Cortex-A9 MPCore
- 1 GByte DDR3 SDRAM (2 x 16-Bit wide 512 MByte DDR3 SDRAM)
- 32 MByte QSPI Flash memory
- 2 x Hi-Speed USB2.0 ULPI transceiver PHY
- 2 x Gigabit (10/100/1000 Mbps) Ethernet transceiver PHY
- 4 GByte eMMC (optional up to 64GByte)
- 2 x MAC-Address EEPROMs
- optional 2 x 8 MByte HyperRAM (max 2 x 32 MByte HyperRAM)
- optional 2 x 32 MByte HyperFLASH
- Temperature compensated RTC (real-time clock)
- Si5338 PLL for GTX Transceiver clocks
- Plug-on module with 3 x 160-pin high-speed strips
- 16 GTX high-performance transceiver lanes
- GT transceiver clock inputs
- 254 FPGA I/O's (125 LVDS pairs)
- On-board high-efficiency DC-DC converters
- System management
- eFUSE bit-stream encryption
- AES bit-stream encryption
- Evenly-spread supply pins for good signal integrity
- User LED
Assembly options for cost or performance optimization available upon request.
Signals, Interfaces and Pins
System Controller I/O Pins
Special purpose pins to configure and operate the System Controller CPLD (IC U14) used by TE0782
Name | Note |
---|---|
BOOTMODE | |
CONFIGX | |
JTAGENB | |
RESIN | |
M_TDO | CPLD JTAG-Interface |
M_TDI | CPLD JTAG-Interface |
M_TCK | CPLD JTAG-Interface |
M_TMS | CPLD JTAG-Interface |
CLPD_GPIO0 | user GPIO |
CLPD_GPIO1 | user GPIO |
CLPD_GPIO2 | user GPIO |
CLPD_GPIO3 | user GPIO |
CLPD_GPIO4 | user GPIO |
CLPD_GPIO5 | user GPIO |
Boot Modes
TE0782 supports primary boot from
- JTAG
- SPI Flash
Boot from on-board eMMC is also supported as secondary boot (FSBL must be loaded from SPI Flash).
The boot modes are controlled by the Pins 'BOOTMODE' and '?' on the board to board (B2B) connector.
BOOTMODE | ? | Boot mode |
---|---|---|
LOW | LOW | JTAG |
LOW | HIGH | SPI (also eMMC as secondary boot) |
HIGH | LOW | |
HIGH | HIGH |
JTAG
JTAG access to the Xilinx Zynq-7000 device is provided by connector J3.
Signal | B2B Pin |
---|---|
TCK | J3: 141 |
TDI | J3: 147 |
TDO | J3: 148 |
TMS | J3: 1142 |
JTAGENB pin in J2 should be kept low or grounded for normal operation.
Clocking
Clock | Frequency | IC | FPGA | Notes |
---|---|---|---|---|
PS CLK | 33.3333 MHz | U61 | PS_CLK | PS Subsystem main clock |
10/100/1000 Mbps ETH PHYs reference | 25 MHz | U11 | - | |
USB PHY reference | 52 MHz | U7 | - |
Processing System (PS) Peripherals
Peripheral | IC | Designator | PS | MIO | Notes |
---|---|---|---|---|---|
- | |||||
- | |||||
- | |||||
- | |||||
- | |||||
SPI Flash | S25FL256SAGBHI20 | U13 | QSPI0 | MIO1..MIO6 | |
Ethernet0 10/100/1000 Mbps PHY | 88E1512-A0-NNP2I000 | U3 | ETH0 | MIO16...MIO27 | |
Ethernet0 10/100/1000 Mbps PHY Reset | GPIO | MIO51 | |||
USB | USB3320C-EZK | U11 | USB0 | MIO28...MIO39 | |
USB Reset | GPIO | MIO49 | |||
e-MMC (embedded e-MMC) | MTFC4GMVEA-4M IT | U5 | SDIO0 | MIO40...MIO45 |
Default MIO mapping
MIO | Configured as | B2B | Notes |
---|---|---|---|
0 | GPIO | J2-87 | B2B |
1 | QSPI0 | - | SPI Flash-CS |
2 | QSPI0 | - | SPI Flash-DQ0 |
3 | QSPI0 | - | SPI Flash-DQ1 |
4 | QSPI0 | - | SPI Flash-DQ2 |
5 | QSPI0 | - | SPI Flash-DQ3 |
6 | QSPI0 | - | SPI Flash-SCK |
7 | GPIO | - | Red LED D8 |
8 | - | - | QSPI feedback clock |
9 | GPIO | J2-88 | B2B |
10 | I2C0 SDA | J2-90 | B2B |
11 | I2C0 SCL | J2-92 | B2B |
12 | I2C1 SDA | J2-93 | B2B (SDA on-board I2C, also configurable as GPIO by user) |
13 | I2C1 SCL | J2-95 | B2B (SCL on-board I2C, also configurable as GPIO by user) |
14 | USART0 RX | J2-94 | B2B (RX on-board UART, also configurable as GPIO by user) |
15 | USART0 TX | J2-96 | B2B (TX on-board UART, also configurable as GPIO by user) |
16..27 | ETH0 | Ethernet RGMII PHY | |
28..39 | USB0 | USB ULPI PHY | |
40 | SDIO0 | J2-100 | |
41 | SDIO0 | J2-102 | |
42 | SDIO0 | J2-104 | |
43 | SDIO0 | J2-106 | |
44 | SDIO0 | J2-108 | |
45 | SDIO0 | J2-110 | |
46 | GPIO | - | RTC Interrupt |
47 | - | - | - |
48 | GPIO | SEL_SD | SD Card multiplexer control |
49 | GPIO | - | USB Reset |
50 | GPIO | - | ETH0 Interrupt |
51 | GPIO | - | ETH0 Reset |
52 | ETH0 | - | MDC |
53 | ETH0 | - | MDIO |
I2C Interface
The on-board I2C components are connected to IO_L1P_T0AD0P_35 (I2C_SDA and) IO_L1N_T0AD0N_35 (I2C_SCL).
I2C addresses for on-board components
Device | IC | Designator | I2C-Address | Notes |
---|---|---|---|---|
EEPROM | 24LC128-I/ST | U26 | 0x53 | ?? |
EEPROM | 24AA025E48T-I/OT | U22 | 0x50 | MAC Address |
EEPROM | 24AA025E48T-I/OT | U24 | 0x51 | MAC Address |
RTC | ISL12020MIRZ | U17 | 0x6F | Temperature compensated real time clock |
Battery backed RAM | ISL12020MIRZ | U17 | 0x57 | integrated in RTC |
CLOCK GENERATOR | SI5338A-B-GMR | U2 | 0x70 | |
CPLD | LCMXO2-1200HC-4TG100I | U14 | user ?? |
B2B I/O
Number of I/O's connected to the SoC's I/O bank and B2B connector
Bank | Type | B2B | IO count | IO Voltage | Notes |
---|---|---|---|---|---|
500 | MIO | J2-87 J2-88 | 2 | 3,3 V | MIO0, MIO9 |
500 | MIO | J2-93 J2-95 J2-94 J2-96 | 4 | 3,3 V | configured as I2C1 and USART0 by default, configurable as GPIO by user |
13 | HR | J1 | 48 | user | |
33 | HR | J1 | 48 | user | |
35 | HR | J2 | 30 | 3,3 V | |
34 | GPIO | J2 | 10 | 2,5 V | configured as DISP_RX by default, configurable as GPIO by user |
For detailed information about the pin out, please refer to the Master Pinout Table.
Peripherals
LED's
There are 3 LED's on TE0729:
LED | Color | Connected to | Notes |
---|---|---|---|
D1 | red | System Controller | Global Status LED |
D2 | green | DONE | Inverted DONE, ON when FPGA not configured |
D8 | red | MIO7 | OFF when PS7 not booted and not controlling MIO7 by software, else user controlled |
LED D2 is connected to the FPGA Done pin and will go off as soon as PL is configured.
This LED will not operate if the System Controller can not power on the 3.3V output rail that also powers the 3.3V circuitry on the module.
Ethernet
The TE0729 is equipped with a Marvell Alaska 88E1512 Gigabit Ethernet PHY (U3) and has in this TRM the identifier Ethernet0. The Ethernet0 PHY RGMII Interface is connected to the Zynq ETH0 PS GEM0. The I/O Voltage is fixed at 1.8V for HSTL signaling.
SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector J2.
The reference clock input of the PHY is supplied from an on board 25MHz oscillator (U10).
Ethernet0 PHY connection:
PHY PIN | ZYNQ PS | ZYNQ PL | Notes |
---|---|---|---|
MDC/MDIO | MIO52, MIO53 | - | - |
LED0 | - | - | pin J2-57 on B2B connector |
LED1 | - | - | pin J2-59 on B2B connector |
LED2/Interrupt | MIO46 | - | - |
CONFIG | - | - | Pin connected to GND, PHY Address is strapped to 0x00 by default |
RESETn | MIO51 | - | - |
RGMII | MIO16..MIO27 | - | - |
SGMII | - | - | on B2B J2 connector |
MDI | - | - | on B2B J2 connector |
The TE0729 SoM is also equipped with two additional Microchip KSZ8081MLXCA Ethernet-PHYs (ICs U17 and U19) to provide further 10/100 Mbps Ethernet interfaces with the identifiers Ethernet1 and Ethernet2. Those PHYs can be operated as Ethernet interfaces 10Base-T or 100Base-T with for 4-wires twisted pair cable. The reference clock input of both PHYs is supplied from the same 25MHz oscillator (U10), which also provides Ethernet0 Gigabit PHY with a reference clock signal.
Ethernet1 PHY connection to B2B-connectors:
PHY PIN | B2B | notes |
---|---|---|
ETH1_RX_P | J2-26 | - |
ETH1_RX_N | J2-28 | - |
ETH1_TX_P | J2-20 | - |
ETH1_TX_N | J2-22 | - |
ETH1_LED0 | J2-34 | Status LED |
ETH1_LED1 | J2-32 | Transmission LED |
Ethernet2 PHY connection to B2B-connectors:
PHY PIN | B2B | notes |
---|---|---|
ETH2_RX_P | J2-2 | - |
ETH2_RX_N | J2-4 | - |
ETH2_TX_P | J2-8 | - |
ETH2_TX_N | J2-10 | - |
ETH2_LED0 | J2-16 | Status LED |
ETH2_LED1 | J2-14 | Transmission LED |
All other pins of the PHYs are connected to Bank34 of Zynq, see schematic for further details.
USB
The USB PHY USB3320 from Microchip is used on the TE0729. The ULPI interface is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V.
The reference clock input of the PHY is supplied from an on board 52MHz oscillator (U12).
PHY connection:
PHY Pin | Zynq Pin | B2B Name | Notes |
---|---|---|---|
ULPI | MIO28..39 | - | Zynq USB0 MIO pins are connected to the PHY |
REFCLK | - | - | 52MHz from on board oscillator (U12) |
REFSEL[0..2] | - | - | 000 GND, select 52MHz reference Clock |
RESETB | MIO49 | - | Active low reset |
CLKOUT | MIO36 | - | Connected to 1.8V selects reference clock operation mode |
DP,DM | - | OTG_D_P, OTG_D_N | USB Data lines |
CPEN | - | VBUS_V_EN | External USB power switch active high enable signal |
VBUS | - | USB_VBUS | Connect to USB VBUS via a series resistor. Check reference schematic |
ID | - | OTG_ID | For an A-Device connect to ground, for a B-Device left floating |
The schematic for the USB connector and required components is different depending on the USB usage. USB standard A or B connectors can be used for Host or Device modes. A Mini USB connector can be used for USB Device mode. A USB Micro connector can be used for Device mode, OTG Mode or Host Mode.
RTC
An Intersil temperature compensated real time clock IC ISL12020MIRZ is used for timekeeping (U22). Battery voltage must be supplied to the module from the main board.
Battery backed registers are accessed at I2C slave address 0x57.
General purpose RAM is accessed at I2C slave address 0x6F.
This RTC IC is supported in Linux so it can be used as hwclock device.
MAC-Address EEPROMs
Three Microchip 24AA025E48 EEPROMs (U8, U9, U20) are used on the TE0729. They contain globally unique 48-bit node addresses, that are compatible with EUI-48(TM) and EUI-64(TM). The devices are organized as two blocks of 128 x 8-bit memory. One of those blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible through the I2C slave address 0x50 for MAC-Address1 (U8), 0x81 for MAC-Address2 (U9), 0x82 for MAC-Address3 (U20).
Power
For startup, a power supply with minimum current capability of 3A is recommended.
VIN and 3.3VIN can be connected to the same source (3.3 V).
Power Supplies
Supply Voltage | Voltage Range | note |
---|---|---|
Vin | 3.3 V to 5.5 V | Typical 200 mA, depending on customer design and connections |
Vin 3.3V | 3.3 V | Typical 50 mA, depending on customer design and connections |
Bank Voltages
Bank | Voltage | max. Value | note |
---|---|---|---|
501 | 1,8 V | - | ETH0 / USB0 / SDIO0 |
500 | 3,3 V | - | SPI / I2C / UART |
502 | 1,5 V | - | DDR3-RAM |
13 | user | 3,3 V | connected to 3,3V by default by 0-Ohm-Resistor R36 |
33 | user | 3,3 V | connected to 3,3V by default by 0-Ohm-Resistor R55 |
34 | 2,5 V | - | ETH / DISP |
35 | 3,3 V | - | GPIO |
Initial Delivery state
Storage device name | Content | Notes |
---|---|---|
24AA025E48 EEPROMs | User content not programmed | Valid MAC Address from manufacturer |
e-MMC Flash-Memory | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash OTP Area | Empty, not programmed | Except serial number programmed by flash vendor |
SPI Flash Quad Enable bit | Programmed | |
SPI Flash main array | demo design | |
EFUSE USER | Not programmed | |
EFUSE Security | Not programmed |
Hardware Revision History
Revision | Changes |
---|---|
01 | Prototypes |
02 | First production release |
Technical Specification
Absolute Maximum Ratings
Parameter | Min | Max | Units | Notes |
---|---|---|---|---|
Vin supply voltage | -0.3 | 6.0 | V | |
Vin33 supply voltage | -0.4 | 3.6 | V | |
VBat supply voltage | -1 | 6.0 | V | |
PL IO Bank supply voltage for HR I/O banks (VCCO) | -0.5 | 3.6 | V | |
I/O input voltage for HP I/O banks | -0.55 | VCCO_X+0.55 | V | TE0729 does not have HP banks |
Voltage on Module JTAG pins | -0.4 | VCCO_0+0.55 | V | VCCO_0 is 3.3V nominal |
Storage Temperature | -40 | +85 | C | |
Storage Temperature without the ISL12020MIRZ | -55 | +100 | C |
Recommended Operating Conditions
Parameter | Min | Max | Units | Notes | Reference document |
---|---|---|---|---|---|
Vin supply voltage | 2.5 | 5.5 | V | ||
Vin33 supply voltage | 3.135 | 3.465 | V | ||
VBat supply voltage | 2.7 | 5.5 | V | ||
PL IO Bank supply voltage for HR I/O banks (VCCO) | 1.14 | 3.465 | V | Xilinx document DS191 | |
I/O input voltage for HR I/O banks | (*) | (*) | V | (*) Check datasheet | Xilinx document DS191 and DS187 |
Voltage on Module JTAG pins | 3.135 | 3.465 | V | VCCO_0 is 3.3 V nominal |
Physical Dimensions
Module size: 76 mm × 52 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 8mm
PCB thickness: 1.6mm
Highest part on PCB: approx. 2.5 mm. Please download the step model for exact numbers.
All dimensions are shown in mm.
Temperature Ranges
Commercial grade modules
All parts are at least commercial temperature range of 0°C to +70°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Industrial grade modules
All parts are at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Weigt | Part |
---|---|
g | Plain module |
g | Set of bolts and nuts |
Document Change History
date | revision | authors | description |
---|---|---|---|
2006-06-14 | v10 | initial release |
Disclaimer
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