TE0701 CPLD

Overview

CPLD Device with designator U14: LCMX02-1200HC

Feature Summary

• Power Management
• Reset Management
• Boot Mode Controller
• FPGA UART routing
• I2C
• LED

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Functional Description

Dip Switch

^*Note that JTAGMODE signal does not work for the PCB REV06 or older. But it will work for PCB REV07 or newer, which is not produced yet.

JTAG

JTAGEN set CPLD of the carrier board TE0701 into the chain for firmware update. In normal mode JTAG is routed directly to the SoC module. Set S3-ENJTAG (S3-C) dip switch to OFF to get access to CPLD of the carrier board.

FMC JTAG is currently not enabled.

Power

EN1 is set to logical one .

EN_FMC is set to logical one or is controlled by I2C on I2C Mode.

PG_C2M is set to logical one or is controlled by I2C on I2C Mode.

VADJ

VADJ on PCB REV06+ S4 Control

This mode is only available on PCB Revision 06 or higher.

S4 control will be enabled on power on sequence or reset (S2-Button), if one of the three S4-DIP switches is set to one.

In this Mode I2C-controll is not selectable and S3-M1 and S3-M2 are available as User-DIP-Switch.

In the new firmware (CPLD firmware Version 07) the VADJ can not be adjustable via I2C more. This voltage can be selected only via S4 dip switch as shown: 

VADJ on PCB REV05- S3 Control

S4 control will be disabled on power on sequence or reset (S2-Button), if all of the three S4-DIP switches is set to OFF or older PCB revision is used.

VADJ on I2C Control

Disable S4 Control (see VADJ on PCB REV05- S3 Control) and set S3-M1 and S3-M2 to on. I2C VADJ Control use TE0701 HDMI I2C Bus (HDMI_SCL and HDMI_SDA) connected to module FPGA PL side. I2C-GPIO controller device address is 0x22. Transmitted data will be converted to a 8-bit GPIO bus.

To read I2C with petalinux use i2cget -y 0 0x22.

• -y: do not confirm input
• 0: I2CBUS, use bus number, which is connected to TE0701 HDMI I2C Bus (HDMI_SCL and HDMI_SDA)
• 0x22 I2C GPIO controller on TE0701 CPLD

To write I2C with petalinux use i2cset -y 0 0x22 0x80

• -y: do not confirm input
• 0: I2CBUS, use bus number, which is connected to TE0701 HDMI I2C Bus (HDMI_SCL and HDMI_SDA)
• 0x22 I2C GPIO controller on TE0701 CPLD
• 0x80: Enable FMC Power with VAD 3.3V, see I2C control table.

Reset

RESIN (negative Reset) to module, can be set by S2 button.

Boot Mode

Boot mode is set to SD-Boot, when SD-Card is detected.

FMC I2C

"3 wire split i2c" to to normal I2C:

FMC_SDA       <= '0' when Y5='0' else 'Z';
FMC_SCL       <= Y0 and PON;
Y1            <= FMC_SDA;

I2C Interface

To read I2C with petalinux use i2cget -y 0 0x22.

• -y: do not confirm input
• 0: I2CBUS, use bus number, which is connected to TE0701 HDMI I2C Bus (HDMI_SCL and HDMI_SDA)
• 0x22 I2C GPIO controller on TE0701 CPLD

To write I2C with petalinux use i2cset -y 0 0x22 0x80

• -y: do not confirm input
• 0: I2CBUS, use bus number, which is connected to TE0701 HDMI I2C Bus (HDMI_SCL and HDMI_SDA)
• 0x22 I2C GPIO controller on TE0701 CPLD
• 0x80: Enable FMC Power with VAD 3.3V, see I2C control table.

RGPIO

RGPIO Master is a 32Bit Remote GPIO Interface to talk with FPGA over 3 lanes.

LED

UART

It is two UART interfaces for Microchip modules and only one UART interface for AMD modules.  For Microchip modules the UART interface be multiplexed between UART0 (HSS console) and UART1 (Linux console) via S1 user pushbutton. By booting in the beginning UART0 is connected to the UART interface ny default. The user can swith to UART1 (Linux console) by pressing the S1 pushbutton any time and vice versa. For microchip modules the *.jed file is special and the CPLD chip of the carrier board must be reprogrammed for this purpose.

Appx. A: Change History

Revision Changes

•  Changes REV06 to REV07:
  • UART interface UART0 only for Microchip modules added
  • S1 is used for multiplexing UART0 and UART1 for Microchip modules.
  • LEDs and PHY_LEDs function is changed.
  • I2C interface with 0x30 address  is added. It is connected to MIO10 (SCL) and MIO11 (SDA).
  • I2C interface with 0x22 address for HDMI chip is changed. It is connected to HDMI_SCL and HDMI_SDA.
  • CPLD_REVISION as generic parameter is added.
  • PGOOD is used as boot mode selector pin in addition to MODE pin (SD_DETECT). In addition to SD card /QSPI boot modes JTAG and eMMC boot modes can be selected. 
  • PGOOD, NOSEQ can be set or reset via CM2 (S4-D) and CM1 (S3-A) respectively. 
  • FMC_VADJ voltage can not be changed via firmware more. This variable votlage can be changed only via S4-A,B,C only.
  • The CPLD of module can be programmed for REV07 or newer versions. JTAGMODE pin is added. JTAGMODE signal can be controlled with CM0 (S3-B) for PCB REV07 or newer versions. 
  • RGPIO is not used more.

• Changes REV05 to REV6:

  •  Connecting PGOOD to CM2 to use as boot mode pin selector

  •  JTAG timing correction

• Changes Older Revisions to REV05:

  • Power Management

    • three VADJ Control Modi (REV06+ S4 Control, REV05- S3 Control and I2C Control)

  • Reset Management

    • only little changes

  • RGPIO Interface to FPGA

    • RGPIO support

  • LED

    • new Order and accessible by RGPIO

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

Appx. B: Legal Notices