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The Trenz Electronic TE0716 is a commercial-grade SoM (System on Module) based on Xilinx Zynq-7000 SoC XC7Z020, with 1GB of DDR3L-1600 SDRAM, 32MB of SPI flash memory, 10x 12-Bit Low Power SAR ADCs, 512Kb Serial EEPROM, Gigabit Ethernet PHY transceiver, a USB PHY transceiver and powerful switching-mode power supplies for all on-board voltages.
Refer to http://trenz.org/te0716-info for the current online version of this manual and other available documentation.
Storage device name | IC Designator | Content | Notes |
---|---|---|---|
Quad SPI Flash | U7 | Empty | - |
512Kb Serial EEPROM | U21 | Empty | - |
2Kb 24AA025E48 EEPROM | U24 | Pre-programmed globally unique, 48-bit node address (MAC). | - |
4Kb M93C66-R EEPROM | U40 | Xilinx JTAG Programmer License | - |
Boot process.
The TE0716 supports QSPI and SD Card boot modes, which is controlled by the insertion of the SD card before powering on.
SD Card State | Boot Mode | Notes |
---|---|---|
SD card inserted | SD Card (J2) | - |
SD card not present | QSPI (U7) | - |
Reset process.
The nRST signal active low reset input, forces PS_POR_B to apply a master reset of the entire Zynq. This reset could be manually done by pressing a switch. This signal could be also reached by a B2B large connector.
This nRST signal (active low) is also held until all FPGA power supplies set their Power Good signals.
Furthermore, if the FPGA core voltage drops under 0.84V or the 3.3V power supply drops to 2.94V or less, this nRST signal is also activated by the Voltage Monitor.
See more about the Power-on Reset (PS_POR_B) signal in the “Zynq-7000 SoC Technical Reference Manual” (“UG585”).
Signal | B2B | I/O | Note |
---|---|---|---|
nRST | JP2-4 | - | - |
nRST | - | S3 | - |
Zynq SoC's I/O banks signals connected to the B2B connectors:
FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
---|---|---|---|---|
MIO 500 | JP1 | 2 | 3.3V | - |
HR 35 | JP1 | 48 | 3.3V | - |
HR 13 | JP2 | 50 | 3.3V | - |
HR 33 | JP2 | 22 | 3.3V | - |
JTAG access to the TExxxx SoM through B2B connector JMX.
JTAG Signal | B2B Connector |
---|---|
TMS | JP2-7 |
TDI | JP2-11 |
TDO | JP2-10 |
TCK | JP2-8 |
MIO Pin | Connected to | B2B | Notes |
---|---|---|---|
15 | UART_TX_ZYNQ | JP1-70 | Also Connected to U36-2. To use this signal from B2B connector, "UART_OB_DISABLE" (JP1-11) must be "High". |
14 | UART_RX_ZYNQ | JP1-71 | Also Connected to U36-3. To use this signal from B2B connector, "UART_OB_DISABLE" (JP1-11) must be "High". |
Test Point | Signal | Connected to | Notes |
---|---|---|---|
TP1 | +1.0V | - | |
TP2 | ADC_VAA | - | |
TP3 | +1.5V | - | |
TP4 | +1.8V | - | |
TP5 | VTT | - | |
TP6 | VTTREF | - | |
TP7 | +5.0V | - | |
TP8 | +3.3V | - | |
TP9 | +5.0V_VAA | - | |
TP10 | +3.3V_ADC | - | |
TP11 | GND | - | |
TP12 | GND | - | |
TP13 | SPI-DQ3/M0 | ||
TP14 | GND |
Chip/Interface | Designator | Notes |
---|---|---|
On-board 32MByte QSPI flash memory S25FL256S (U7) could be used to store the initial FPGA configuration file. After configuration completes, the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.
MIO Pin | Schematic | U7 Pin | Notes |
---|---|---|---|
The TE0716 module has 10x 12-Bit Low Power SAR Analog-to-Digital Converter, fully differential input, signed output, with SPI−compatible interface (NCD98011), which are connected to the FPGA PL BANK34.
MIO Pin | Schematic | U? Pin | Notes |
---|---|---|---|
MIO Pin | I2C Address | Designator | Notes |
---|---|---|---|
MAC-Address EEPROM
A 2Kbit 24AA025E48 serial EEPROM I2C memory (U24), connected to the BANK501 PSMIOs, contains a globally unique 48-bit node address, which is compatible with EUI-48TM specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks, the upper half of the array (80h-FFh), stores the 48-bit node address and is permanently write-protected, while the other block is available for application use.
MIO Pin | Schematic | U?? Pin | Notes |
---|---|---|---|
General Purpose EEPROM
I2C Device | I2C Address | Designator | Notes |
---|---|---|---|
2K Serial EEPROMs with EUI-48™ | 0xA6 (write) | U24 | |
512Kb Serial EEPROM | 0xA0 (write) | U21 |
Designator | Color | Connected to | Active Level | Note |
---|---|---|---|---|
The TE0716 module has two 500MByte DDR3L SDRAM chips (U12 & U13) arranged into 32-bit wide memory bus providing total on-board memory size of 1GByte.
U?? Pin | Signal Name | Connected to | Signal Description | Note |
---|---|---|---|---|
Bank | Schematic | U?? Pin | Notes |
---|---|---|---|
D-Tx | Driver Input | ||
R-Rx | Reciever Output |
Designator | Description | Frequency | Note |
---|---|---|---|
MHz | |||
MHz | |||
KHz | |||
There is a programmable clock generator on-board (U??) provided in order to generate variable clocks for the module. Programming can be done using I2C via PIN header J??. The I2C Address is 0x??.
U?? Pin | Signal | Connected to | Direction | Note |
---|---|---|---|---|
IN0 | ||||
IN1 | ||||
IN2 | ||||
IN3 | ||||
XAXB | ||||
SCLK | ||||
SDA | ||||
OUT0 | ||||
OUT1 | ||||
OUT2 | ||||
OUT3 | ||||
OUT4 | ||||
OUT5 | ||||
OUT6 | ||||
OUT7 | ||||
OUT8/OUT9 |
Power supply with minimum current capability of xx A for system startup is recommended.
Power Input Pin | Typical Current |
---|---|
VIN | TBD* |
* TBD - To Be Determined
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Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | B2B Connector JM3 Pin | Direction | Notes |
---|---|---|---|---|---|
Bank | Schematic Name | Voltage | Notes |
---|---|---|---|
? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.
3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)
Operating Temperature: -??°C ~ ??°C
Current Rating: ??A per ContactNumber of Positions: ??
Number of Rows: ??
Symbols | Description | Min | Max | Unit |
---|---|---|---|---|
V | ||||
V | ||||
V | ||||
V | ||||
V | ||||
V | ||||
V | ||||
V | ||||
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
V | See ???? datasheets. | |||
V | See Xilinx ???? datasheet. | |||
V | See Xilinx ???? datasheet. | |||
V | See Xilinx ???? datasheet. | |||
V | See Xilinx ???? datasheet. | |||
V | See Xilinx ???? datasheet. | |||
V | See Xilinx ???? datasheet. | |||
°C | See Xilinx ???? datasheet. | |||
°C | See Xilinx ???? datasheet. |
Module size: ?? mm × ?? mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ? mm.
PCB thickness: ?? mm.
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Trenz shop TEXXXX overview page | |
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English page | German page |
Date | Revision | Changes | Documentation Link |
---|---|---|---|
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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Date | Revision | Contributor | Description |
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