Trenz Electronic use different memory types for TE0630 Modules with different size.
| Manufacturer | Device Name | Article Name Identification Code(1) | Size |
|---|---|---|---|
| Nanya | NT5CC64M16GP-DII | 1 | 128MB |
| ISSI | IS43TR16256BL-125KBLI | 2 | 512MB |
(1) assembled memory can be identified by their article name according to encoding table on Digit/Letter at position 14, see:
This page demonstrates MPMC setup for each memory and one single configuration to support both memory with the same design.
Spartan 6 Memory Controller IPs
- MPMC Version 6.06a (Multi Port Memory Controller)
- MIG Version Version 1.06.a
TE0630 Design uses MPMC Version 6.06a IP to configure the MCB. This is used for DMA access of the FX2 IP. Design is created with EDK.
Memory configuration
Maximum DDR3 Speed for Spartan 6:
- DS162 page 18
- 667Mb/s for Speedgrade -2; 800 possible for Speedgrade -3
Shared memory configuration | NT5CC64M16GP-DII | IS43TR16256BL-125KBLI | |
|---|---|---|---|
| Manufacturer | Nanya/ISSI | Nanya | ISSI |
| Total Size | 128MB | 128MB | 512MB |
| Number of DIMMs | 1 | ||
| Memory Data Width | 16 | ||
| ODT Setting | RZQ/6 | ||
| Reduced Drive Output | RZQ/6 | ||
| Dynamic Write ODT Setting | DIV4 | ||
| Auto Self Refresh | Enabled | ||
| High Temp Self Refresh | Extended | ||
| Memory Clock Periode | Auto | ||
| Data Depth | 64 | 64 | 256 |
| Data Width | 16 | ||
| Bank Bits | 3 | ||
| Row Bits | 13 | 13 | 15 |
| Column Bits | 10 | ||
CAS Lat. A Fmax CAS Latency max frequency | 333MHz | ||
| CAS Lat. B-D Fmax | auto | ||
| CAS Lat. A CAS Latency | 6(*) | 6(**) | 5 |
| CAS Lat. B-D | auto | ||
| tZQINIT (tCK) Power-up and RESET calibration time | 512 | ||
| tZQCS (tCK) Normal operation Short calibration time | 64 | ||
| tRRD (ps) ACTIVE to ACTIVE command period for 1KB | 12000(*) | ||
| tMRD (tCK) Mode Register Set command cycle time | 4 | ||
| tRCS (ps) ACT to internal read or write delay | 13125(*) | ||
| tCCD CAS# to CAS# command delay | 4 | ||
| tWR (ps) WRITE recovery time | 15000 | ||
| tWTR (ps) Delay from start of internal write transaction to internal read command | 12000(*) | ||
| tREFI (ps) Average periodic refresh interval | 7800000 | ||
| tRFC (ps) All Bank Refresh to active/refresh cmd time | 260000(*) | 110000 | 260000 |
| tRP (ps) PRE command period | 13125(*) | ||
| tRC (ps) ACT to ACT or REF command period | 50625 | ||
| tRASMAX (ps) Maximum ACTIVE-to-PRECHARGE command | 70200000 | ||
| tRAS (ps) ACT to PRE command period | 37500 | ||
| MCB ZIO Pin Location | F13 | ||
| MCB RZQ Pin Location | F15 | ||
| Skip Input Termination Calibration | disabled | ||
| Skip Dynamic Calibration | disabled | ||
| Skip Dynamic Input Termination | enabled | ||
- (*) Changed parameter settings compared to the reference designs setup from 2012
- (**) 2012 reference design use CL 5 for NT5CC64M16GP-DII which work well but it's not supported by memory data sheet of this device
The following data sheets were used to verify timing configuration:
Nanya:
- NT5CC64M16GP-DII_1gb_ddr3_g_die_component_datasheet.pdf
- "DDR3(L) 1Gb SDRAM NT5CB(C)128M8GN / NT5CB(C)64M16GP"
- Version: 2.4 09/2019
ISSI:
- IS43TR16256BL-125KBLI_43-46TR16256B-85120BL.pdf
- "IS43/46TR16256B, IS43/46TR16256BL,IS43/46TR85120B, IS43/46TR85120BL"
- Version: REV. D1 07/11/2024
Overview
Content Tools