Overview

Board Overview

Power supply

Over Micro USB or VIN Pin (5V) possible.

JTAG/UART

JTAG and UART connections are available through Micro USB connector.  External JTAG Programmer is not needed.

Pin name

Connected to

DirectionNote
BDBUS0E18inuart rx
BDBUS1F16outuart tx
UART

Push Buttons

  • Reset Button: reset Cyclone V (connected to nCONFIG Pin)
  • User Button: connected to FPGA Pin L17

LEDs

There are 2 status LEDs and 8 user LEDs which can be used for variant purposes.


NameColorConnected toActive LevelNote
Power LEDGreen3.3Vlow3.3V status LED
CONF_DONERedCONF_DONE pinhigh--
LED1RedP4high--
LED2RedM4high--
LED3RedM3high--
LED4RedN3high--
LED5RedV2high--
LED6RedT2high--
LED7RedL1high--
LED8RedK1high--
Module LEDs

CRUVI Pin Header J3

The Pin Header J3 is based on CRUVI Standard. For more information, please visit www.cruvi.com.

The Pins of the pin header J3 are connected to the FPGA Bank 7A and 8A. With the VSEL pin (connected to N10) the voltage of these banks (VADJ) must be selected between 1.8V and 3.3V (depends on connected periphery):

VSEL

VADJ voltage

Note
01.8V--
13.3V--
VSEL

Reference Designs

Notes




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