TesKit is a "Test Fixture" for testing TE0808, most I/O pins are looped back for I/O Connector connectivity testing. For additional testing an LVDS oscillator is providing known clock to GT Reference Clock. SMA Connectors are provided on PL and on PS Connected GT lanes. Connector is provided for direct connection to SiLabs ClockBuilder Pro Field Programmer for Si5345 Programming.
Item | Name | Vendor | Separate Order | Comments |
---|---|---|---|---|
1 | TE0808 or TE803 | Trenz | TE0808, TE0803 | |
3 | TE0790 USB JTAG/UART Adapter | Trenz | TE0790 | |
4 | SMA Cable (50 cm long), 4 pcs | |||
5 | mini USB Cable | |||
6 | Cables for power (2mm Banana Connector), 2 pcs | |||
7 | ClockBuilder Pro Programmer | SiLabs | digikey / mouser |
NOTE: Kit Content may be different, depending on customer agreements. Positions 1 to 3 are always included.
Supported Bootmodes are SPI and JTAG.
TestKits are pre-assembled and pre-flashed with initial Flash image, they start up as soon as power (3.3V) is applied.
Power would be around 3W if the ZU+ does not boot (DDR4 not active), with Linux booted (or hello world from DDR4) then power consumption goes up to some 5W, if the junction temperature goes higher power consumption goes up to 6-7W.
Depending on initial Flash content either Hello appears, or then Linux does boot.
To restart the boot process press the small push-button on TE0790, it is wired to TE0808 Reset.
TesKit808, mini-USB cable not connected, 3.3V power applied.
TE0790 SW | TE0808 RLED | TE0790 GLED | TE0790 RLED | DONE | ERR |
---|---|---|---|---|---|
Pressed | OFF | ON | ON | OFF | OFF |
Released | OFF | ON | ON | ON | ON |
GT transceiver have either internal connection or loopbacks or are connected to SMA Connectors. Note that connections to SMA are not AC Coupled!
QUAD | Lane | Function |
---|---|---|
B128 | 0 | on-board loopback |
B128 | 0 | B505 Lane 1 |
B128 | 1 | B505 Lane 2 |
B128 | 2 | B505 Lane 3 |
B228 | 0-3 | on-board loopback |
B229 | 0-3 | on-board loopback |
B230 | 0-2 | on-board loopback |
B230 | 3 | SMA Connectors |
B505 | 0 | SMA Connectors |
B505 | 1 | B128 Lane 0 |
B505 | 2 | B128 Lane 1 |
B505 | 3 | B128 Lane 2 |
GT Transceiver connections and loopbacks.
PL I/O has on-board internal loopback an all pins for connectivity testing.
UART is available on MIO68, MIO69 via the supplied TE0790 USB Module. TE0808 and TE0803 board parts do not support this settings. They must be changed manually.
M3 | M2 | M1 | M0 | Bootmode Hex | Bootmode | Notes |
---|---|---|---|---|---|---|
ON | ON | ON | ON | 0x0 | PS Main JTAG (TE0790 USB JTAG) | Needed for SPI Flash Programming |
ON | ON | OFF | ON | 0x2 | SPI Flash (dual parallel, 4bit x 2, 32bit Addressing) | Default |
Flash programming is supported from SDK GUI, fsbl.elf that is needed is provided in common download area.
See Xilinx AR66715
Please check Project Delivery first.
This works out of the box with Vivado/SDK 2016.1, if you only have EVAL license for ZU+ then it is necessary to export HDF without bitstream.
Support in Petalinux 2016.x for ZU+ MPSoC is fully integrated. Vivado HSI flow works, all settings from Vivado Design are imported to SDK and Petalinux to generate a working system with all required software components.
Important: BL31.ELF is needed or Linux would fail with kernel panic. PMU Fimware is not absolutely necessary, without it there would be warnings during Linux boot.
Note: if there are no network drivers installed, then linux boot does stop on "Configuring network interfaces..." as workaround special "disable network" application can be installed into petalinux to allow booting with no network.
If Si5345 is not programmed then there is only 1 GT Clock available, from 125MHz oscillator on TEBT0808, it does clock B228 CLK0 input, with this clock up to 12 GT can be tested, including the GT that has SMA connectors.
IBERT with external Loopback on QUAD228, using 125MHz LVDS clock from TEBT0808 base.
Setup for Si5345 PLL Programming using SiLabs ClockBuilder Pro Field Programmer.
Date | Revision | Contributors | Description |
---|---|---|---|
2017-06-07 | John Hartfiel | Initial version. |
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