Table of Contents
Overview
The Trenz Electronic TE0725LP is a low cost small-sized FPGA module integrating a Xilinx Artix-7 and 32 MByte Flash memory for configuration and operation.
Key Features
Xilinx Artix-7 XC7A100T
32 MByte Flash memory
2 x 50-pin headers with 2,54mm pitch, ideal for breadboard use
- 92 x GPIOs (42 + 42 + 8)
- 25.000000 MHz system clock
- I2C EEPROM
3.3V single power supply with on-board voltage regulators
JTAG/UART connector
1 user LED
- Optional HyperRAM (8 to 32 MByte)
- Commercial temperature grade (Industrial on Request)
- Size 73 x 35 mm
Block Diagram
Main Components
Note on the images below, that there is no POF transceiver, no 50-pin headers and no JTAG/UART header installed.
- Xilinx Artix-7 FPGA, U1
- 32-MByte Flash memory, U7
- Low VIN high-efficiency step-down converter, U5
- Low VIN high-efficiency step-down converter, U6
- POF transceiver placeholder, U8
- 50-pin placeholder for breadboard connector, J1
- 50-pin placeholder for breadboard connector, J2
- JTAG/UART connector, JB1
- Red LED (SYSLED), D2
- 16K x 8 (128-Kbit) serial EEPROM, U2
- Low-noise, high PSRR, RF, 200-mA low-dropout linear regulator, U9
- Ultra-low supply-current voltage monitor with optional watchdog, U6
- Cypress S27KS0641 64-Mbit (8-MByte) HyperRAM™ self-refresh DRAM, U4
Signals, Interfaces and Pins
I/O Banks
Bank | VCCIO | B2B I/O | Notes |
---|---|---|---|
0 | 3.3V | 0 | JTAG |
14 | 3.3V | 0 (3) | 3 I/O in XMOD-JTAG - for use as UART |
15 | 1.8V | 0 | used for optional hyper RAM |
16 | 2.5V | 0 | used for optional optical fiber transceiver |
34 | User select | 42 | 0R resistor option to select 3.3V |
35 | User select | 42 | 0R resistor option to select 3.3V |
JTAG Interface
JTAG access to the Xilinx Artix-7 device is provided through connector JB1.
Signal | Pin Number |
---|---|
TCK | JB1-4 |
TDO | JB1-8 |
TDI | JB1-10 |
TMS | JB1-12 |
Connector JB1 (2 x 6 pin header) is compatible with XMOD JTAG adapter TE0790. This adapter can be inserted from top onto the TE0725LP, if JB1 is fitted with male pin header. Optionally JB1 can be fitted with pin header from bottom, in that case the JTAG cable connector must be on the base board.
When using XMOD-JTAG in JB1 then additionally USB UART is usable, and the push-button on XMOD works as configuration reset.
When using XMOD-JTAG please check the switch settings on XMOD to be sure the power and I/O reference are supplied correctly. TE0790 can be in some cases used to power up TE0725LP, however this is not recommended. TE0790-01 can not supply enough power for TE0725LP (LED may blink but the module is not operating properly, especially in case of larger and more sophisticated designs).
On-board LED's
LED | Color | FPGA | Notes |
---|---|---|---|
D2 | Green | M16 | |
D3 | Red | DONE | Active low |
Connectors
All connectors are are for 100mil headers, all connector locations are in 100 mil grid.
LED | Color | FPGA | Notes |
---|---|---|---|
D2 | Green | M16 | |
D3 | Red | DONE | Active low |
Power and Power-On Sequence
To power-up a module, power supply with minimum current capability of 1A is recommended.
Power Supply
TE0725LP needs one single power supply with nominal of 3.3V.
Power Consumption
FPGA | Design | Typical Power, 25C ambient |
---|---|---|
A100T | Not configured | TBD* |
*TBD - To Be Determined.
Actual power consumption depends on the FPGA design and ambient temperature.
Power-On Sequence
There is no specific or special power-on sequence, single power source is needed as VIN, rest of the sequence is automatic.
Variants Currently In Production
Module Variant | FPGA Chip Model | PL Clock | VIN Supply Voltage |
---|---|---|---|
TE0725LP-01-100-2C | XC7A100T-2CSG324C | 25 MHz | 3.3 V |
TE0725LP-01-100-2D | XC7A100T-2CSG324C | 25 MHz | 1.8 V |
TE0725LP-01-100-2L | XC7A100T-2CSG324C | 25 MHz | 1.8 V |
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Reference document |
---|---|---|---|---|
3.3V supply voltage | -0.1 | 3.6 | V | |
HR I/O banks supply voltage (VCCO) | -0.5 | 3.6 | V | Xilinx datasheet DS181 |
HR I/O banks input voltage | -0.4 | VCCO + 0.55 | V | Xilinx datasheet DS181 |
Storage Temperature | -40 | +85 | °C |
Recommended Operating Conditions
Parameter | Min | Max | Units | Reference document |
---|---|---|---|---|
VIN supply voltage | 3.135 | 3.45 | V | |
HR I/O banks supply voltage (VCCO) | 1.14 | 3.465 | V | Xilinx datasheet DS181 |
HR I/O banks input voltage | -0.20 | VCCO + 0.20 | V | Xilinx datasheet DS181 |
Operating Temperature | 0 | +85 | °C |
Physical Dimensions
Please note that two different units are used on the figures below, SI system millimeters (mm) and imperial system thousandths of an inch(mil). This is because of the 100mil pin headers used, see also explanation below. To convert mils to millimeters and vice versa use formula 100mil's = 2,54mm.
All 100 mil pin headers are in 100 mil grid, the M3 mounting holes are in 50 mil grid aligned to the centers of the 100mil headers. The module is symmetrical, turning it 180 degrees will keep all I/O and Power pins in both 50 pin headers in compatible places.
Operating Temperature Ranges
Commercial grade modules
All parts conform to at least commercial temperature range of 0°C to +70°C.
Industrial grade modules
All parts are at least industrial temperature range of -40°C to +85°C.
The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Weight
8.5 g Plain module.
Revision History
Hardware Revision History
Date | Revision | Notes | PCN | Documentation Link |
---|---|---|---|---|
2016-07-21 | 01 | Prototypes |
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
Document Change History
Date | Revision | Contributors | Description |
---|---|---|---|
2017-08-17 | Jan Kumann | Initial version. |
Disclaimer
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