Table of contents
Overview
Firmware for PCB-Master CPLD with designator U5: LCMX02-1200HC.
Feature Summary
- Power Management
- Reset Management
- LED Control
Firmware Revision and supported PCB Revision
See Document Change History
Product Specification
Port Description
Name / opt. VHD Name | Direction | Pin | Description |
---|---|---|---|
200MHZCLK_EN | out | 30 | |
BUTTON | in | 77 | Reset Button |
CPLD_JTAG_TCK | 91 | not accessible as IO | |
CPLD_JTAG_TDI | 94 | not accessible as IO | |
CPLD_JTAG_TDO | 95 | not accessible as IO | |
CPLD_JTAG_TMS | 90 | not accessible as IO | |
DDR3_SCL | 43 | / currently_not_used | |
DDR3_SDA | 42 | / currently_not_used | |
DONE | in | 18 | FPGA Done |
EN_1V8 | out | 58 | Power Enable |
EN_3V3FMC | out | 60 | Power Enable |
EN_FMC_VADJ | out | 51 | Power Enable |
F1PWM | out | 98 | |
F1SENSE | in | 99 | / currently_not_used |
FEX_DIR | 19 | / currently_not_used | |
FEX0 | out | 12 | PERST from PCIe slot |
FEX1 | 15 | / currently_not_used | |
FEX10 | 4 | / currently_not_used | |
FEX11 | in | 10 | User LED |
FEX2 | 13 | / currently_not_used | |
FEX3 | 9 | / currently_not_used | |
FEX4 | 3 | / currently_not_used | |
FEX5 | 7 | / currently_not_used | |
FEX6 | 24 | / currently_not_used | |
FEX7 | 17 | / currently_not_used | |
FEX8 | 21 | / currently_not_used | |
FEX9 | 25 | / currently_not_used | |
FMC_PG_C2M | 69 | / currently_not_used | |
FMC_PG_M2C | 68 | / currently_not_used | |
FMC_PRSNT_M2C_L | 70 | / currently_not_used | |
FMC_SCL | 49 | / currently_not_used | |
FMC_SDA | 48 | / currently_not_used | |
FMC_TCK | 27 | / currently_not_used | |
FMC_TDI | 31 | / currently_not_used | |
FMC_TDO | 32 | / currently_not_used | |
FMC_TMS | 28 | / currently_not_used | |
FMC_TRST | 36 | / currently_not_used | |
FPGA_IIC_OE | 14 | ||
FPGA_IIC_SCL | 1 | ||
FPGA_IIC_SDA | 16 | ||
LED1 | out | 76 | Status LED D1 (green) |
LTM_1V_IO0 | 86 | Power Good | |
LTM_1V_IO1 | 88 | Power Good | |
LTM_1V5_4V_IO0 | 85 | Power Good | |
LTM_1V5_4V_IO1 | 83 | Power Good | |
LTM_1V5_RUN | 74 | / currently_not_used | |
LTM_4V_RUN | 75 | / currently_not_used | |
LTM_SCL | 67 | / currently_not_used | |
LTM_SDA | 66 | / currently_not_used | |
LTM1_ALERT | 65 | / currently_not_used | |
LTM2_ALERT | 64 | / currently_not_used | |
PCIE_RSTB | in | 37 | PERST from PCIe card edge connector |
PG_1V8 | in | 59 | Power Good |
PG_3V3 | in | 61 | Power Good |
PG_FMC_VADJ | in | 52 | Power Good |
PLL_SCL | 2 | SI5338 | |
PLL_SDA | inout | 8 | SI5338 |
PROGRAM_B | out | 20 | FPGA PROG_B |
VID0_FMC_VADJ | out | 53 | FMC EN5365QI power selection pin |
VID1_FMC_VADJ | out | 54 | FMC EN5365QI power selection pin |
VID2_FMC_VADJ | out | 57 | FMC EN5365QI power selection pin |
Functional Description
JTAG
CPLD JTAG is always enabled.
Power
Power sequence on will be executed over 4 States:
- State 1 IDLE: Wait until LTM_1V_IO0 (1V), LTM_1V_IO1 (1V) and LTM_1V5_4V_IO1 (4V) is available.
- State 2 PS1: Enables 1V8, 3V3FMC and VADJ. Wait until PG_1V8 (1.8V), PG_3V3 (3.3V) and PG_FMC_VADJ (FMC VADJ) is available.
- State 3 PS2: Wait until LTM_1V5_4V_IO0 (1.5V) is available
- State 4 RDY: All power on
State machine restart power sequencing, if on of the power good signal are lost.
FMC VADJ is set to 1.8V.
Reset
PROGRAM_B is controlled by push button after power up sequencing is ready.
CLK
200MHz CLK is enabled after power up.
Si5338 configuration is not implemented.
Button
Button is debounced and controls PROG_B signal from FPGA.
LED
LED is used as Status LED for power management and programming. Status depends on blink sequence.
Status | Blink sequence | Comment |
---|---|---|
Error - Power IDLE state | ******** | Reset or Main Power Problem |
Error - Power PS1 state | *****ooo | Periphery Power Problem (1.8V, 3.3V, FMC VADJ) |
Error - Power PS2 state | ****oooo | DDR Bank Power Problem (1.5V) |
Power Ready, FPGA not programmed | ***ooooo | ~0,7 Hz, duty cycle 3/8 |
-- | **oooooo | ~0,7 Hz, duty cycle 2/8, currently not used |
-- | *ooooooo | ~0,7 Hz, duty cycle 1/8, currently not used |
User Mode | user defined | Power Ready, FPGA programmed, LED is accessible over FEX11 |
Appx. A: Change History and Legal Notices
Revision Changes
CPLD REV01 to REV02
- BUGFIX: PCIe Reset
- USER LED accessible
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
---|---|---|---|---|---|
REV02 | REV01 | REV02 working in process | |||
2017-08-06 | v.4 | REV01 | REV01 | John Hartfiel | REV01 finished |
2017-05-29 | v.1 | --- | Initial release | ||
All |
Appx. A: Legal Notices
Data Privacy
Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy
Document Warranty
The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.
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Technology Licenses
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