Table of Contents
Overview
The Trenz Electronic TE0725LP is a low cost small-sized FPGA module integrating a Xilinx Artix-7 and 32 MByte Flash memory for configuration and operation.
Key Features
Xilinx Artix-7 XC7A100T FPGA
32 MByte Flash memory
2 x 50-pin headers with 2,54mm pitch, ideal for breadboard use
- 92 x GPIOs (42 + 42 + 8)
- 25.000000 MHz system clock
- I2C EEPROM for FPGA bitstream
3.3V single power supply with on-board voltage regulators
JTAG/UART connector
1 user LED
- Optional HyperRAM (8 to 32 MByte)
- Commercial temperature grade (Industrial on Request)
- Size 73 x 35 mm
Block Diagram
Main Components
- Xilinx Artix-7 FPGA, U1
- 128K I2C CMOS serial EEPROM, U2
- Low-power programmable oscillator @25.000000 MHz, U3
- Cypress S26KS512S 512-Mbit (64-MByte) 1.8V HyperFlash™ memory, U4
- Low VIN high-efficiency step-down converter (1.5A max.), U5
- Low VIN high-efficiency step-down converter (1.5A max.), U6
- 1.8V, 256-MBit (32-MByte) quad SPI serial flash memory, U7
- Ultra-low supply-current voltage monitor with optional watchdog, U8
- 50-pin header placeholder for breadboard connector, J1
- 50-pin header placeholder for breadboard connector, J2
- 14-pin header placeholder for connector, J3
- JTAG/UART connector, JB1
- Red LED (SYSLED), D2
Initial Delivery State
| On-board Programmable Device | Content | Notes |
|---|---|---|
| Quad SPI Flash OTP area | Empty | |
| I2C EEPROM, U2 | Empty |
Boot Process
Boot...
Signals, Interfaces and Pins
Board to Board (B2B) I/Os
I/O signals connected to the SoCs I/O bank and B2B connector:
| Bank | Type | B2B Connector | I/O Signal Count | Bank Voltage |
|---|---|---|---|---|
| 34 | HR | J2 | 42 I/Os, 21 LVDS pairs | VCCIO34 |
| 35 | HR | J1 | 42 I/Os, 21 LVDS pairs | VCCIO35 |
Table x: General overview of PL I/O signals connected to the B2B connectors.
I/O Banks
| Bank | VCCIO | B2B I/O | Notes |
|---|---|---|---|
| 0 | 3.3V | 0 | JTAG |
| 14 | 3.3V | 0 (3) | 3 I/O in XMOD-JTAG - for use as UART |
| 15 | 1.8V | 0 | Used for optional hyper RAM |
| 34 | User select | 42 | 0R resistor option to select 3.3V |
| 35 | User select | 42 | 0R resistor option to select 3.3V |
JTAG Interface
JTAG access to the Xilinx Artix-7 device is provided through connector JB1.
| Signal | Pin Number |
|---|---|
| TCK | JB1-4 |
| TDO | JB1-8 |
| TDI | JB1-10 |
| TMS | JB1-12 |
Connector JB1 (2 x 6 pin header) is compatible with XMOD-JTAG adapter TE0790. This adapter can be inserted from top onto the TE0725LP, if JB1 is fitted with male pin header. Optionally JB1 can be fitted with pin header from bottom, in that case the JTAG cable connector must be on the base board.
When XMOD-JTAG is connected to the JB1, then additionally USB UART is available, and the push-button on the XMOD works as configuration reset.
When using XMOD-JTAG please check its DIP-switch S2 settings to be sure that correct power and I/O reference voltages ares set. TE0790 can be in some cases used to power up TE0725LP, however this is not recommended. TE0790-01 can not supply enough power for TE0725LP (LED may blink but the module is not operating properly, especially in case of larger and more sophisticated FPGA designs).
On-board LEDs
There is one red LED connected to the FPGA bank 14, pin M16.
| LED | Color | FPGA | Notes |
|---|---|---|---|
| D2 | Red | M16 | SYSLED |
Connectors
All connectors are are for 100mil headers, all connector locations are in 100 mil grid.
Power and Power-On Sequence
To power-up a module, power supply with minimum current capability of 1A is recommended.
Power Supply
TE0725LP needs one single power supply with nominal of 3.3V.
Power Consumption
| FPGA | Design | Typical Power, 25C ambient |
|---|---|---|
| A100T | Not configured | TBD* |
*TBD - To Be Determined.
Actual power consumption depends on the FPGA design and ambient temperature.
Power-On Sequence
There is no specific or special power-on sequence, single power source is needed as VIN, rest of the sequence is automatic.
Variants Currently In Production
| Module Variant | FPGA Chip Model | PL Clock | VIN Supply Voltage |
|---|---|---|---|
| TE0725LP-01-100-2C | XC7A100T-2CSG324C | 25 MHz | 3.3 V |
| TE0725LP-01-100-2D | XC7A100T-2CSG324C | 25 MHz | 1.8 V |
| TE0725LP-01-100-2L | XC7A100T-2CSG324C | 25 MHz | 1.8 V |
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Units | Reference document |
|---|---|---|---|---|
3.3V supply voltage | -0.1 | 3.6 | V | |
| HR I/O banks supply voltage (VCCO) | -0.5 | 3.6 | V | Xilinx datasheet DS181 |
| HR I/O banks input voltage | -0.4 | VCCO + 0.55 | V | Xilinx datasheet DS181 |
Storage Temperature | -40 | +85 | °C |
Recommended Operating Conditions
| Parameter | Min | Max | Units | Reference document |
|---|---|---|---|---|
| VIN supply voltage | 3.135 | 3.45 | V | |
| HR I/O banks supply voltage (VCCO) | 1.14 | 3.465 | V | Xilinx datasheet DS181 |
| HR I/O banks input voltage | -0.20 | VCCO + 0.20 | V | Xilinx datasheet DS181 |
| Operating Temperature | 0 | +85 | °C |
Please check Xilinx datasheet DS181 for complete list of absolute maximum and recommended operating ratings for the Artix-7 device.
Physical Dimensions
Please note that two different units are used on the figures below, SI system millimeters (mm) and imperial system thousandths of an inch(mil). This is because of the 100mil pin headers used, see also explanation below. To convert mils to millimeters and vice versa use formula 100mil's = 2,54mm.
All 100 mil pin headers are in 100 mil grid, the M3 mounting holes are in 50 mil grid aligned to the centers of the 100mil headers. The module is symmetrical, turning it 180 degrees will keep all I/O and Power pins in both 50 pin headers in compatible places.
Operating Temperature Ranges
Commercial grade modules
All parts conform to at least commercial temperature range of 0°C to +70°C.
Industrial grade modules
All parts are at least industrial temperature range of -40°C to +85°C.
The module operating temperature range depends on customer design and cooling solution. Please contact us for options.
Weight
8.5 g Plain module.
Revision History
Hardware Revision History
| Date | Revision | Notes | PCN | Documentation Link |
|---|---|---|---|---|
| 2016-07-21 | 01 | Prototypes |
Hardware revision number is printed on the PCB board together with the module model number separated by the dash.
Document Change History
| Date | Revision | Contributors | Description |
|---|---|---|---|
Jan Kumann | Initial version. |
Disclaimer
Data Privacy
Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy
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WEEE
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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
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