TE0725LP TRM

Overview

The Trenz Electronic TE0725LP is a low cost small-sized FPGA module integrating a Xilinx Artix-7 and 32 MByte Flash memory for configuration and operation.

Key Features

• Xilinx Artix-7 XC7A100T FPGA

• 32 MByte QSPI Flash memory

• 2 x 50-pin headers with 2,54mm pitch, ideal for breadboard use

• 92 x GPIOs (42 + 42 + 8)
• 25.000000 MHz system clock
• 128 KBit (16 KByte) I²C EEPROM
  

• 3.3V single power supply with on-board voltage regulators

• JTAG/UART connector 

• 1 user LED

• Optional HyperRAM (8 to 32 MByte)
• Commercial temperature grade (Industrial on Request)
• Size 73 x 35 mm

Block Diagram

Figure 1: TE0725LP-01 Block Diagram.

Main Components

Figure 2: TE0725LP-01 FPGA module (Variant TE0725LP-01-100-2D depicted).

1. XMOD header, JB1
2. 14-pin header placeholder for connector, J3
3. Xilinx Artix-7 FPGA, U1
4. 1.8V, 256 MBit (32 MByte) quad SPI serial flash memory, U7
5. Red LED (SYSLED), D2
6. Cypress S26KS512S 512 MBit (64 MByte) 1.8V HyperFlash™ memory, U4 (optional)
7. Low-power programmable oscillator @25.000000 MHz, U3
8. Low VIN high-efficiency step-down converter (1.5A max.), U5
9. Low VIN high-efficiency step-down converter (1.5A max.), U6 (optional)
10. 50-pin header placeholder for breadboard connector, J1
11. 50-pin header placeholder for breadboard connector, J2
12. Ultra-low supply-current voltage monitor with optional watchdog, U8
13. 128KBit I²C CMOS serial EEPROM, U2

Initial Delivery State

Table 1: Module initial delivery state of programmable on-board devices.

Boot Process

By default the configuration mode pins of the FPGA are set to Master SPI mode, hence the FPGA is configured from serial QSPI flash memory at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the QSPI flash memory.

Signals, Interfaces and Pins

I/Os on Pin Headers

I/O signals of the FPGA SoC's I/O banks connected to the board's pin headers:

Table 2: General overview of single ended and LVDS I/O signals connected to pin headers

PL I/O-Banks

Table 3: General overview of PL I/O-bank signals.

JTAG Interface

JTAG access to the Xilinx Artix-7 device is provided through XMOD header JB1.

Header JB1 (2 x 6 pin) is compatible with XMOD-JTAG adapter TE0790. This adapter can be inserted from top onto the TE0725LP, if JB1 is fitted with male pin header. Optionally JB1 can be fitted with pin header from bottom, in that case the JTAG connector must be on the base board.

XMOD FTDI JTAG-Adapter Header JB1

The JTAG interface of the FPGA can be accessed via XMOD header JB1, so in use with the XMOD-FT2232H adapter-board TE0790 the FPGA can be configured via USB2.0 interface. The TE0790 board provides also an UART interface to the FPGA device which can be accessed by the USB2.0 interface of the adapter-board while the signals between these serial interfaces will be converted.

Following table describes the signals and interfaces of the XMOD header JB1:

Table 4: XMOD header JX1 signals and connections.

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCCIO will be sourced by the FPGA module's supply voltage (1.8V). The adapter board's VCC has to be sourced by the USB Host interface.

For this configuration, set the XMOD DIP-switch as follows in table below:

Table 5: XMOD adapter board DIP-switch positions for voltage configuration.

UART Interface

UART interface is available on B2B connector JM2. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:

Table 6: UART interface signals.

QSPI Interface

The QSPI interface of the FPGA device is routed to and used by the on-module QSPI flash IC U7:

Table 7: QSPI interface signals.

I2C Interface

The I²C interface of the FPGA device is routed to and used by the on-module EEPROM IC U2:

Table 8: I²C interface signals.

Differential Analog Input

The TE0725LP FPGA module provides access to the XADC (Analog-to-Digital Converter) unit of the Xilinx FPGA via connector J3:

Table 9: XADC interface signals.

On-board Peripherals

Quad SPI Flash Memory

On-module QSPI flash memory (U7) is provided by Micron Serial NOR Flash Memory N25Q256A with 256 MBit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

HyperFlash™ Memory

On the TE0725LP FPGA module is optionally available a Cypress S26KS512S 512 MBit (64 MByte) 1.8V HyperFlash™ memory IC (U4). This flash memory IC is connected to the FPGA bank 15 via the Cypress specific HyperBus interface, which offers read bandwidth up to 333MByete/s.

EEPROM

A Microchip 24AA128 128 KBit (16 KByte) CMOS Serial EEPROM (U2). The device is organized as eight blocks of 16 KBit memory with a 2-wire serial interface connected on FPGA bank 14. The memory as  is available for application use. It is accessible over I²C bus with slave device address 0x50.

System Clock Oscillator

A low-power SiTime programmable oscillator (U3) @25.000000 MHz configured on-module is connected to PL I/O-bank 14 and provides the system reference clock signal.

On-board LEDs

There is one red LED connected to the FPGA bank 14, pin M16. This LED is user configurable to indicate for example any system status.

Table 10: LEDs of the module.

Connectors

All connectors are are for 100mil headers, all connector locations are in 100mil (2.54mm) grid. The module's PCB provides footprints to mount and solder optional (B2B connector) headers, if those are not factory-fitted on module.

Power and Power-On Sequence

To power-up a module, power supply with minimum current capability of 1A is recommended.

Power Supply

TE0725LP needs one single power supply with nominal of 3.3V at the variant TE0725-01-100-2C or 1.8V at the variants TE0725LP-01-100-2D and TE0725LP-01-100-2D. Following diagram shows the dependencies of the power supply:

Figure 3: Module power supply dependencies

Power Consumption

Table 11: Module power consumption

*TBD - To Be Determined.

Actual power consumption depends on the FPGA design and ambient temperature.

Power-On Sequence

There is no specific or special power-on sequence, single power source is needed as VIN.

Voltage Monitor Circuit

The 1.8V voltage level is monitored by the voltage monitor circuit U8, which generates the PROG_B signal to begin a new configuration sequence after reset of the FPGA. A manual reset is also possible by driving the connector pin JB1-11 ('NRST') to GND. Hence, by this pin a mounted XMOD adapter board can perform a reset on the FPGA module.

Figure 4: Voltage monitor circuit

Power Rails

Table 13: Board power rails

Bank Voltages

Table 14: Board bank voltages

Variants Currently In Production

Table 12: Module variants production

Technical Specifications

Absolute Maximum Ratings

Table 13: Absolute maximum ratings

Recommended Operating Conditions

Table 14: Recommended operating conditions

Physical Dimensions

Please note that two different units are used on the figures below, SI system millimeters (mm) and imperial system thousandths of an inch(mil). This is because of the 100mil pin headers used, see also explanation below. To convert mils to millimeters and vice versa use formula 100mil's = 2,54mm.

• Board size: PCB 72.9mm ×  34.8mm

• PCB thickness: ca. 1.65mm

• Highest part on the PCB are the pin headers (2.54mm pitch). Please download the step model for exact numbers.

 The dimensions are given in mm and mil (milli inch).

Figure 5: Module physical dimensions drawing

Revision History

Hardware Revision History

Table 15: Module hardware revision history

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Figure 6: Module hardware revision number

Document Change History

Date	Revision	Contributors	Description
Error rendering macro 'page-info' Ambiguous method overloading for method jdk.proxy244.$Proxy3557#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]		Ali Naseri, Jan Kumann	First TRM release

Table 16: Document change history

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