You are viewing an old version of this page. View the current version.

Compare with Current View Page History

« Previous Version 40 Next »

Table of Contents

Overview

The Trenz Electronic TE0725LP is a low cost small-sized FPGA module integrating a Xilinx Artix-7 and 32 MByte Flash memory for configuration and operation.

Key Features

  • Xilinx Artix-7 XC7A100T FPGA

  • 32 MByte QSPI Flash memory

  • 2 x 50-pin headers with 2,54mm pitch, ideal for breadboard use

  • 92 x GPIOs (42 + 42 + 8)
  • 25.000000 MHz system clock
  • 128 KBit (16 KByte) I2C EEPROM
  • 3.3V single power supply with on-board voltage regulators

  • JTAG/UART connector 

  • 1 user LED

  • Optional HyperRAM (8 to 32 MByte)
  • Commercial temperature grade (Industrial on Request)
  • Size 73 x 35 mm

Block Diagram

Figure 1: TE0725LP-01 Block Diagram.

Main Components

Figure 2TE0725LP-01 FPGA module (Variant TE0725LP-01-100-2D depicted).

  1. XMOD header, JB1
  2. 14-pin header placeholder for connector, J3
  3. Xilinx Artix-7 FPGA, U1
  4. 1.8V, 256 MBit (32 MByte) quad SPI serial flash memory, U7
  5. Red LED (SYSLED), D2
  6. Cypress S26KS512S 512 MBit (64 MByte) 1.8V HyperFlash™ memory, U4 (optional)
  7. Low-power programmable oscillator @25.000000 MHz, U3
  8. Low VIN high-efficiency step-down converter (1.5A max.), U5
  9. Low VIN high-efficiency step-down converter (1.5A max.), U6 (optional)
  10. 50-pin header placeholder for breadboard connector, J1
  11. 50-pin header placeholder for breadboard connector, J2
  12. Ultra-low supply-current voltage monitor with optional watchdog, U8
  13. 128KBit I2C CMOS serial EEPROM, U2


Initial Delivery State

On-board Programmable DeviceContentNotes
Quad SPI Flash (U7) OTP areaEmpty-
I2C EEPROM, U2Empty-
HyperFlash™ memory, U4Empty-

Table 1: Module initial delivery state of programmable on-board devices.

Boot Process

By default the configuration mode pins of the FPGA are set to Master SPI mode, hence the FPGA is configured from serial QSPI flash memory at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the QSPI flash memory.

Signals, Interfaces and Pins

I/Os on Pin Headers

I/O signals of the FPGA SoC's I/O banks connected to the board's pin headers:

BankTypePin HeaderI/O Signal CountBank Voltage
14HRJ38 I/O's, 4 LVDS pairs1.8V
34HRJ242 I/Os, 21 LVDS pairsVCCIO34
35HRJ142 I/Os, 21 LVDS pairsVCCIO35

Table 2: General overview of single ended and LVDS I/O signals connected to pin headers

PL I/O-Banks

BankVCCIOI/O's CountAvailable On ConnectorsNotes
03.3V744 I/O's used for JTAG interface, 3 control signals (DONE, PROG_B, INIT).
143.3V12118 I/O's (4 LVDS pairs) connected to J3, 3 I/O's to XMOD header JB1 (2 UART I/O's, 1 user I/O), 1 I/O to LED D2.
151.8V18-Used for optional HyperFlash™ U4.
34User select42420-Ohm resistor R17 option to select 1.8V I/O-bank VCCIO.
35User select42420-Ohm resistor R25 option to select 1.8V I/O-bank VCCIO.

Table 3: General overview of PL I/O-bank signals.

JTAG Interface

JTAG access to the Xilinx Artix-7 device is provided through XMOD header JB1.

Header JB1 (2 x 6 pin) is compatible with XMOD-JTAG adapter TE0790. This adapter can be inserted from top onto the TE0725LP, if JB1 is fitted with male pin header. Optionally JB1 can be fitted with pin header from bottom, in that case the JTAG connector must be on the base board.

XMOD FTDI JTAG-Adapter Header JB1

The JTAG interface of the FPGA can be accessed via XMOD header JB1, so in use with the XMOD-FT2232H adapter-board TE0790 the FPGA can be configured via USB2.0 interface. The TE0790 board provides also an UART interface to the FPGA device which can be accessed by the USB2.0 interface of the adapter-board while the signals between these serial interfaces will be converted.

Following table describes the signals and interfaces of the XMOD header JB1:

Pin Schematic NameXMOD Header JB1 PinNote
F_TCKC (pin J3-4)-
F_TDOD (pin J3-8)-
F_TDIF (pin J3-10)-
F_TMSH (pin J3-12)-
UART_RXDA (pin J3-3)UART receive line, connected to PL I/O-bank 14.
UART_TXDB (pin J3-7)UART transmit line, connected to PL I/O-bank 14.
XMOD_EE (pin J3-9)User configurable, connected to PL I/O-bank 14, pin M17.
NRSTG (pin J3-11)Assigned to 'PROG_B' (configuration-reset signal of FPGA) via IC U8.

Table 4: XMOD header JX1 signals and connections.

When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCCIO will be sourced by the FPGA module's supply voltage (1.8V). The adapter board's VCC has to be sourced by the USB Host interface.

For this configuration, set the XMOD DIP-switch as follows in table below:

XMOD DIP-switchesPosition
Switch 1ON
Switch 2OFF
Switch 3OFF
Switch 4

ON

Table 5: XMOD adapter board DIP-switch positions for voltage configuration.

Use Xilinx compatible TE0790 adapter board (designation TE-0790-xx with out 'L') to program the Xilinx Zynq devices.

The TE0790 adapter board's CPLD have to be configured with the Standard variant of the firmware. Refer to the TE0790 Resources Site for further information and firmware download.

UART Interface

UART interface is available on B2B connector JM2. With the TE0790 XMOD USB2.0 adapter, the UART signals can be converted to USB2.0 interface signals:

UART Signal Schematic NameB2BXMOD Header JX1Pin Header J3Note
B14_L0JM2-99JX1-7J3-7UART-TX (transmit line)
B14_L25JM2-97JX1-3J3-3UART-RX (receive line)

Table 6: UART interface signals.

QSPI Interface

The QSPI interface of the FPGA device is routed to and used by the on-module QSPI flash IC U7:

SD IO Signal Schematic NameFPGA I/OFlash Memory (U7) PinNote
SPI-DQOBank 14, pin K17D3QSPI data
SPI-DQ1Bank 14, pin K18D2QSPI data
SPI-DQ2Bank 14, pin L14C4QSPI data
SPI-DQ3Bank 14, pin M14D4QSPI data
SPI_SCKBank 0, pin E9B2QSPI clock
SPI-CSBank 14, pin L13C2QSPI chip select

Table 7: QSPI interface signals.

I2C Interface

The I2C interface of the FPGA device is routed to and used by the on-module EEPROM IC U2:

I²C Signal Schematic NameFPGA I/OEEPROM (U2) PinNotes
I2C_SDABank 14, pin U185I²C data line, 1.8V reference voltage
I2C_SCLBank 14, pin U176I²C clock line, 1.8V reference voltage
I2C_WPBank 14, pin T187Write-protect signal of EEPROM

Table 8: I2C interface signals.

Differential Analog Input

The TE0725LP FPGA module provides access to the XADC (Analog-to-Digital Converter) unit of the Xilinx FPGA via connector J3:

I²C Signal Schematic NameFPGA I/OConnector J3 PinNotes
XADC_PBank 0, pin J10 (VP_0)J3-14-
XADC_NBank 0, pin K9 (VN_0)J3-13-

Table 9: XADC interface signals.

On-board Peripherals

Quad SPI Flash Memory

On-module QSPI flash memory (U7) is provided by Micron Serial NOR Flash Memory N25Q256A with 256 MBit (32 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

HyperFlash™ Memory

On the TE0725LP FPGA module is optionally available a Cypress S26KS512S 512 MBit (64 MByte) 1.8V HyperFlash™ memory IC (U4). This flash memory IC is connected to the FPGA bank 15 via the Cypress specific HyperBus interface, which offers read bandwidth up to 333MByete/s.

EEPROM

A Microchip 24AA128 128 KBit (16 KByte) CMOS Serial EEPROM (U2). The device is organized as eight blocks of 16 KBit memory with a 2-wire serial interface connected on FPGA bank 14. The memory as  is available for application use. It is accessible over I2C bus with slave device address 0x50.

System Clock Oscillator

A low-power SiTime programmable oscillator (U3) @25.000000 MHz configured on-module is connected to PL I/O-bank 14 and provides the system reference clock signal.

On-board LEDs

There is one red LED connected to the FPGA bank 14, pin M16. This LED is user configurable to indicate for example any system status.

LEDColorSignal Schematic NameFPGANotes
D2Red'SYSLED'Pin M16-

Table 10: LEDs of the module.

Connectors

All connectors are are for 100mil headers, all connector locations are in 100mil (2.54mm) grid. The module's PCB provides footprints to mount and solder optional (B2B connector) headers, if those are not factory-fitted on module.

Power and Power-On Sequence

To power-up a module, power supply with minimum current capability of 1A is recommended.

Power Supply

TE0725LP needs one single power supply with nominal of 3.3V at the variant TE0725-01-100-2C or 1.8V at the variants TE0725LP-01-100-2D and TE0725LP-01-100-2D. Following diagram shows the dependencies of the power supply:


Figure 3: Module power supply dependencies

Power Consumption

FPGADesignTypical Power, 25C ambient
XC7A100T-2CSG324CNot configuredTBD*

Table 11: Module power consumption

*TBD - To Be Determined.

Actual power consumption depends on the FPGA design and ambient temperature.

Power-On Sequence

There is no specific or special power-on sequence, single power source is needed as VIN.

Voltage Monitor Circuit

The 1.8V voltage level is monitored by the voltage monitor circuit U8, which generates the PROG_B signal to begin a new configuration sequence after reset of the FPGA. A manual reset is also possible by driving the connector pin JB1-11 ('NRST') to GND. Hence, by this pin a mounted XMOD adapter board can perform a reset on the FPGA module.

Figure 4Voltage monitor circuit

Power Rails

Power Rail Name

J1 Pins

J2 PinsJ3 PinsJB1 Pin

Direction

Notes
VIN555-InputPower supply voltage
1.8V---6OutputJTAG VCCIO
1.8V_OUT---6Output-
VCCIO34-6, 45--InputBank voltage
VCCIO356, 45---InputBank voltage

Table 13: Board power rails

Bank Voltages

Bank

Bank I/O Voltage VCCO

Voltage Range

0 (config)1.8Vfixed
14 (HR)1.8Vfixed
15 (HR)1.8Vfixed
34 (HR)VCCIO341.2V ... 3.3V
35 (HR)VCCIO341.2V ... 3.3V

Table 14: Board bank voltages

Variants Currently In Production

Module Variant

FPGA Chip Model

HyperFlash™ Memory (U4)

DC-DC TPS62510 (U6)2x25 Pin Header J12x25 Pin Header J2
TE0725LP-01-100-2CXC7A100T-2CSG324Cfittedfittednot fittednot fitted
TE0725LP-01-100-2DXC7A100T-2CSG324Cnot fittednot fittedfittedfitted
TE0725LP-01-100-2LXC7A100T-2CSG324Cnot fittednot fittednot fittednot fitted

Table 12: Module variants production

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Reference document

VIN supply voltage (Variant TE0725LP-01-100-2C)

-0.3

4

V

TI TPS62510 data sheet
VIN supply voltage (Variant TE0725LP-01-100-2D and -2L)-0.32VXilinx datasheet DS181 / TI TPS62510 datasheet
HR I/O banks supply voltage (VCCO)-0.53.6VXilinx datasheet DS181
HR I/O banks input voltage (VCCIO single ended)-0.4VCCO + 0.55VXilinx datasheet DS181

Storage Temperature

-40

+100

°C

LED SML-P11x series datasheet

Table 13: Absolute maximum ratings

Recommended Operating Conditions

ParameterMinMaxUnitsReference document
VIN supply voltage (Variant TE0725LP-01-100-2C)1.83.8VTI TPS62510 data sheet
VIN supply voltage (Variant TE0725LP-01-100-2D and -2L)1.81.89VXilinx datasheet DS181 / TI TPS62510 datasheet
HR I/O banks supply voltage (VCCO)1.143.465VXilinx datasheet DS181
HR I/O banks input voltage (VCCIO single ended)-0.20VCCO + 0.20VXilinx datasheet DS181
Operating Temperature0+85

°C

Xilinx datasheet DS181

Table 14: Recommended operating conditions

Please check Xilinx datasheet DS181 for complete list of absolute maximum and recommended operating ratings for the Artix-7 device.

Physical Dimensions

Please note that two different units are used on the figures below, SI system millimeters (mm) and imperial system thousandths of an inch(mil). This is because of the 100mil pin headers used, see also explanation below. To convert mils to millimeters and vice versa use formula 100mil's = 2,54mm.

  • Board size: PCB 72.9mm ×  34.8mm

  • PCB thickness: ca. 1.65mm

  • Highest part on the PCB are the pin headers (2.54mm pitch). Please download the step model for exact numbers.

 The dimensions are given in mm and mil (milli inch).

Figure 5: Module physical dimensions drawing

Revision History

Hardware Revision History

DateRevision

Notes

PCNDocumentation Link
-

01

First production release- TE0725LP-01

Table 15: Module hardware revision history

Hardware revision number is printed on the PCB board together with the module model number separated by the dash.

Figure 6: Module hardware revision number

Document Change History

 Date

Revision

ContributorsDescription

Error rendering macro 'page-info'

Ambiguous method overloading for method jdk.proxy244.$Proxy3557#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]

Ali Naseri, Jan Kumann

  • First TRM release

Table 16: Document change history

Disclaimer

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.


Error rendering macro 'page-info'

Ambiguous method overloading for method jdk.proxy244.$Proxy3557#hasContentLevelPermission. Cannot resolve which method to invoke for [null, class java.lang.String, class com.atlassian.confluence.pages.Page] due to overlapping prototypes between: [interface com.atlassian.confluence.user.ConfluenceUser, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject] [interface com.atlassian.user.User, class java.lang.String, class com.atlassian.confluence.core.ContentEntityObject]

  • No labels