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: Attention: Carrier/Module combination only with special condition or PCB modification possible
: Supported
: Supported with limitations
: Not Supported
: Table currently not complete, see TRM of module and carrier
TEBT0865 - Test Carrier for TE0865
| JTAG /UART (SoC/FPGA) over TE0790 JB1 | JTAG (CPLD) over TEI0005 | UART J8 | ETH J11 | USB J12 | Firefly J10 | MIO I2C Pinheader J19 | MIO Pinheader J8 | IO Pinheader J14-J17 | |
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| TE0865 |
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- (1) Default UART0 used on Trenz Reference Design and Board Files
- (2) LVTTL/LVCMOS 3.3V with TEBT0865
- (3) GTY131 Lane 0-3, other MGTs are loopbacked
- (4) only some IOs from Bank 64/65, 66/67, 86, 89/90/91, other IOs are loopbacked
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