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Zynq MPSoC Debug Troubleshooting


#ProblemPossible reason(s)Fix(es) or workaround
1Debug freezes on DDR4 initDDR4 init can be done only once, if the PS DDR4 was initialized then any attempt of double init, by FSBL c code or psu_init.tcl will freezePower cycle or hardware reset is required to clear DDR4 registers
2Debug freezes on SERDES initOn TE0808 Si5345 is not initialized after power-up by default, and if the FSBL was generated from Vivado project that enables any PS GT, then FSBL or psu_init.tcl would freezeProgramming the Si5345 OTP, disabling all PS GT in Vivado, starting an FSBL that does init Si5345 then debugging without power cycle, using Silabs desktop programmer to init Si5345.
3JTAG Target not detected by SDK/DebuggerOn Zynq MPSoC JTAG is disabled by default after each power cycle or main reset and only enabled if bootrom does it under software control. If FSBL is not found or the FSBL found detects some error condition, then JTAG may be left disabled, and further debugging is not possible.Select JTAG bootmode. Use known good FSBL that releases JTAG for debug process.
4SDK FSBL Debugger show only Assembler Code, instead of C CodeBuild and BSP settings are not correct

Change Settings

For fsbl:

  • right click on fsbl, select C/C++ Build settings
  • Select ARM A53 gcc compiler->Miscellaneous
  • remove "-Os -flto -ffat-lto-objects" from 'other flags'

For fsbl_bsp

  • right click on fsbl_bsp and select Board Support Package Settings
  • Select overview->standalone
  • change zynqmp_fsbl_bsp value from 'true' to 'false'

See: https://forums.xilinx.com/t5/Embedded-Development-Tools/Debug-FSBL-with-SDK-on-ZynqMP-ES2/td-p/773403

5

FSBL debug flags: https://www.xilinx.com/support/documentation/user_guides/ug1137-zynq-ultrascale-mpsoc-swdev.pdf


Check ZynqMP Links on Xilinx Answer Record

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