CompanyTrenz Electronic GmbH
PCN NumberPCN-20230101
TitleTE0714-03 to TE0714-04 Hardware Revision Change
SubjectHardware Revision Change
Issue Date

2023-01-17

Products Affected

This change affects all Trenz Electronic TE0714 SoMs: TE0714-03*.

Affected Product

Replacement
TE0714-03-50-2IAC6TE0714-04-52I-8-A
TE0714-03-50-2I TE0714-04-52I-7-B
TE0714-03-35-2IC7TE0714-04-42I-7-C
TE0714-03-35-2I3TE0714-04-42I-7-L
TE0714-03-35-2ITE0714-04-42I-7-B

Changes

#1 Changed DCDCs from TPS82085SIL to MPM3834CGPA-Z for U1 and U19.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None. Minor changes in electrical characteristics.

#2 Changed DCDC from EP5357HUI to MPM3834CGPA for U3.

Type: Schematic Change

Reason: EOL of Component.

Impact: None. Increased current output capability. Minor changes in electrical characteristics.

#3 Changed TPS27081ADDCR to MP5077GG-Z for Q1.

Type: Schematic Change

Reason: BOM Optimization.

Impact: None. Increased current output capability. Minor changes in electrical characteristics.

#4 Changed voltage monitor TPS3805H33DCKR to STM6710LWB6F for U23 and added resistor R38.

Type: Schematic Change

Reason: BOM Optimization.

Impact: Improved power monitoring circuit by supervising additional voltage rails. If monitored voltages are out of range reset is triggered.

#5 Added diode D2 between signals "INIT" and "PROG_BD".

Type: Schematic Change

Reason: Keep FPGA in reset while signal "PROG_B" is low during initial power-up.

Impact: None.

#6 Changed inductors from BKP0603HS121-T to MPZ0603S121HT000 for L1, L2, L10, and L11.

Type: BOM Change

Reason: EOL of component.

Impact: None.

#7 Added voltage translator for signal "EN_GTPWR" (U10, C34, R36, R46).

Type: Schematic Change

Reason: Improve clock enable level for 1.8V versions of TE0714.

Impact: EN high signal imunity to small voltage deviations.

#8 Changed power sequence for U5 and U6.

Type: Schematic Change

Reason: Use Xilinx recommended power sequence.

Impact: None.

#9 Changed voltage rail 1.35V_LDO to 1.4V_LDO and increased voltage accodingly.

Type: Schematic Change

Reason: Improve voltage rail behaviour.

Impact: None.

#10 Updated decoupling capacitors (added C43...46, C53, C60).

Type: Schematic Change

Reason: Improve decoupling according to Xilinx recommendation.

Impact: None.

#11 Removed serial number S/N and use FPGA U4 pins H14, D10, R6, J6 for PCB REV identification.

Type: Schematic Change

Reason: EOL of component.

Impact: Check that these FPGA pins are handled properly.

#12 Added testpoints for 1.0V (TP17 and TP18) and for SENSE net (TP19 and TP20).

Type: Schematic Change

Reason: Improved debugging possibilities.

Impact: None.

#13 Added pull-up resistor R37 and testpoint TP21 for DCDC U6 PG pin.

Type: Schematic Change

Reason: Improved debugging possibilities.

Impact: None.

#14 Added testpoints TP10...16 on top layer.

Type: Schematic Change

Reason: Improved debugging possibilities.

Impact: None.

#15 Added UKCA logo.

Type: PCB Change

Reason: Requiered for export to UK.

Impact: None.

#15 Added RoHS logo.

Type: PCB Change

Reason: Documentation Improvement.

Impact: None.

#16 Added system overview, power diagram, and legal notices.

Type: Documentation Update

Reason: Documentation improvement.

Impact: None.


Method of Identification

The revision number is printed on the top side of the PCB.

Production Shipment Schedule

From August 2023, after old stock is gone. If the new revision is not suitable for your application and still the former revision of the board is needed, please contact us.


Contact Information

If you have any questions related to this PCN, please contact Trenz Electronics Technical Support at

Disclaimer

Any projected dates in this PCN are based on the most current product information at the time this PCN is being issued, but they may change due to unforeseen circumstances.  For the latest schedule and any other information, please contact your local Trenz Electronic sales office, technical support or local distributor.

This PCN follows JEDEC Standard J-STD-046.

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