PCN-20260107 TEI0006-04 to TEI0006-05 Hardware Revision Change

Products Affected

This change affects all Trenz Electronic TEI0006 SoMs of Revision 04: TEI0006-04*.

Changes

#1 Added ZDM mode with 0R resistors as assembly option

Type: Schematic Change
Reason: Add Zero delay mode or optional backwards compatibility with older revisions of TEI0006.
Impact: Default assembly is R49 and R51 not fitted, R166, R167, R168, C181, C182 fitted. This results in former not used CLK9 is looped back to Feedback Input IN3 of U14 for ZDM. Former CLK input from B2B (CLKIN) is now connected to IN1 of U20. Therefore the CLK configuration has to be updated to account for this. If backwards compatibility is needed, a special assembly version has to be ordered where R49, R51 are fitted and R166, R167, R168, C181, C182 not fitted. This results in exact connection as in revision 04.

#2 Added testpoints (TP23..39) on top layer 

Type: Schematic Change
Reason: Improve manual testability for customers.
Impact: All voltages accessible on top layer via testpoints.

#3 Added TPM 2.0 crypto IC ST33KTPM2I3WBZA9 (U20)

Type: Schematic Change
Reason: Add option for additional security features.
Impact: TPM features available.

#4 Added additional bypass capacitors to DDR4 VTT net

Type: Schematic Change
Reason: Respect DDR4 implementation recommendation.
Impact: Improved decoupling.

#5 Changed capacitors X5R to X7R/X6S

Type: BOM change
Reason: Improve temperature range. 
Impact: None, capacitors have slightly larger capacitance variation. 

#6 Added R171 to BST pin of U4

Type: Schematic Change
Reason: Follow MPS datasheet for MP8869S.
Impact: None, BST resistor can be optimised if necessary.

#7 Capacitors C159, C165, C153, C141, C148, C173, C211, C53, C65, C55, C68, C43, C89, C90, C4, C26 replaced with 100nF

Type: BOM change
Reason: BOM optimisation.
Impact: None.

#8 Added resistor R174 (0R) between CPLD and FPGA

Type: Schematic Change
Reason: Improve signal integrity of clock signal (Stub free routing). 
Impact: None, improved routing.

#9 Added optional resistors R175, R176 (0R, DNP) to optionally directly connect I2C bus to FPGA.

Type: Schematic Change
Reason: 1.8V I2C bus  connection to the FPGA (Bank B2A) nets M10_IO3/M10_IO4 is made via 0R resistors (set as DNP).
Impact: None.

Method of Identification

The revision number is printed on the top side of the PCB.

Production Shipment Schedule

From April 2026, after old stock is gone. If the new revision is not suitable for your application and still the former revision of the board is needed, please contact us.

This PCN follows JEDEC Standard J-STD-046.