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Table of contents

Overview

Firmware for PCB CPLD with designator U27. CPLD Device in Chain: LCMX02-7000HC

Feature Summary

  • Power Management
  • Reset Management
  • Boot Mode
  • FAN Control
  • LED Control
  • FMC JTAG
  • CAN
  • PJTAG

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinBank PowerDescriptionSchematic SheetPCB < REV03
3V3SB
B163.3VCPLD Programm Pin connected with pullupSC1
3V3SB
B203.3VCPLD initn Pin connected with pullupSC1
3V3SB
C293.3VCPLD Done Pin connected with pullupSC1
A_LA06_SC_N
C22FMC_AF_1.8V / currently_not_usedSC2
A_LA06_SC_P
B22FMC_AF_1.8V / currently_not_usedSC2
A_LA07_SC_N
F20FMC_AF_1.8V / currently_not_usedSC2
A_LA07_SC_P
E22FMC_AF_1.8V / currently_not_usedSC2
A_LA08_SC_N
E21FMC_AF_1.8V / currently_not_usedSC2
A_LA08_SC_P
D22FMC_AF_1.8V / currently_not_usedSC2
A_LA09_SC_N
G22FMC_AF_1.8V / currently_not_usedSC2
A_LA09_SC_P
G21FMC_AF_1.8V / currently_not_usedSC2
A_LA10_SC_N
G17FMC_AF_1.8V / currently_not_usedSC2
A_LA10_SC_P
H16FMC_AF_1.8V / currently_not_usedSC2
A_LA11_SC_N
K22FMC_AF_1.8V / currently_not_usedSC2
A_LA11_SC_P
K21FMC_AF_1.8V / currently_not_usedSC2
A_LA12_SC_N
H20FMC_AF_1.8V / currently_not_usedSC2
A_LA12_SC_P
H21FMC_AF_1.8V / currently_not_usedSC2
A_LA13_SC_N
L22FMC_AF_1.8V / currently_not_usedSC2
A_LA13_SC_P
L21FMC_AF_1.8V / currently_not_usedSC2
A_LA14_SC_N
G16FMC_AF_1.8V / currently_not_usedSC2
A_LA14_SC_P
F18FMC_AF_1.8V / currently_not_usedSC2
A_LA15_SC_N
D19FMC_AF_1.8V / currently_not_usedSC2
A_LA15_SC_P
C21FMC_AF_1.8V / currently_not_usedSC2
A_LA16_SC_N
M21FMC_AF_1.8V / currently_not_usedSC2
A_LA16_SC_P
M22FMC_AF_1.8V / currently_not_usedSC2
A_LA17_SC_N
N21FMC_AF_1.8V / currently_not_usedSC2
A_LA17_SC_P
N22FMC_AF_1.8V / currently_not_usedSC2
A_LA18_SC_N
G19FMC_AF_1.8V / currently_not_usedSC2
A_LA18_SC_P
F19FMC_AF_1.8V / currently_not_usedSC2
A_LA19_SC_N
E19FMC_AF_1.8V / currently_not_usedSC2
A_LA19_SC_P
D20FMC_AF_1.8V / currently_not_usedSC2
A_LA20_SC_N
E20FMC_AF_1.8V / currently_not_usedSC2
A_LA20_SC_P
D21FMC_AF_1.8V / currently_not_usedSC2
A_LA21_SC_N
J17FMC_AF_1.8V / currently_not_usedSC2
A_LA21_SC_P
J16FMC_AF_1.8V / currently_not_usedSC2
A_LA22_SC_N
J19FMC_AF_1.8V / currently_not_usedSC2
A_LA22_SC_P
J18FMC_AF_1.8V / currently_not_usedSC2
A_LA23_SC_N
G18FMC_AF_1.8V / currently_not_usedSC2
A_LA23_SC_P
H17FMC_AF_1.8V / currently_not_usedSC2
A_LA24_SC_N
R22FMC_AF_1.8V / currently_not_usedSC2
A_LA24_SC_P
P20FMC_AF_1.8V / currently_not_usedSC2
A_LA25_SC_N
K16FMC_AF_1.8V / currently_not_usedSC2
A_LA25_SC_P
K17FMC_AF_1.8V / currently_not_usedSC2
A_LA26_SC_N
K18FMC_AF_1.8V / currently_not_usedSC2
A_LA26_SC_P
L20FMC_AF_1.8V / currently_not_usedSC2
A_LA27_SC_N
K20FMC_AF_1.8V / currently_not_usedSC2
A_LA27_SC_P
J21FMC_AF_1.8V / currently_not_usedSC2
A_LA28_SC_N
U22FMC_AF_1.8V / currently_not_usedSC2
A_LA28_SC_P
T20FMC_AF_1.8V / currently_not_usedSC2
A_LA29_SC_N
T22FMC_AF_1.8V / currently_not_usedSC2
A_LA29_SC_P
T21FMC_AF_1.8V / currently_not_usedSC2
A_LA30_SC_N
W22FMC_AF_1.8V / currently_not_usedSC2
A_LA30_SC_P
V21FMC_AF_1.8V / currently_not_usedSC2
A_LA31_SC_N
V22FMC_AF_1.8V / currently_not_usedSC2
A_LA31_SC_P
U20FMC_AF_1.8V / currently_not_usedSC2
A_LA32_SC_N
Y20FMC_AF_1.8V / currently_not_usedSC2
A_LA32_SC_P
Y21FMC_AF_1.8V / currently_not_usedSC2
A_LA33_SC_N
AA22FMC_AF_1.8V / currently_not_usedSC2
A_LA33_SC_P
Y22FMC_AF_1.8V / currently_not_usedSC2
B64_T1outD31.8Vreserved for RGPIO  / currently_not_implementedSC2
B64_T2inC31.8Vreserved for RGPIO / currently_not_implementedSC2
B64_T3inB11.8Vreserved for RGPIO / currently_not_implementedSC2
B65_T1inC21.8VCAN_S (with pulldown)SC2
B65_T2outE41.8VCAN_FAULT SC2
B65_T3
C11.8V / currently_not_usedSC2
B66_T1inD11.8VFPGA / dp_aux_data_outSC2
B66_T2inF41.8VFPGA / dp_aux_data_oe_nSC2
B66_T3outF31.8VFPGA / dp_aux_data_SC2
B67_T1outF11.8VFPGA / dp_hot_plug_detectSC2
B67_T2inG31.8VFPGA /  LED SC2
B67_T3inH41.8VFPGA / LED SC2
C_TCKinA83.3VJTAG  CPLD XMODSC1
C_TDIinC73.3V

JTAG CPLD XMOD

 
SC1
C_TDOoutA63.3VJTAG CPLD XMODSC1
C_TMSintC93.3VJTAG CPLD XMODSC1
CAN_FAULTinD153.3VCAN / B65_T2SC1
CAN_RXinB153.3VCAN / MIO34SC1
CAN_SoutC153.3VCAN /  B65_T1 SC1
CAN_TXoutC163.3VCAN / MIO35SC1
CLK_SCinAA93.3Vexternal User CLK 25MHz (oscillator is assembly option)SC1
DDR_ENoutC63.3VPower 7ASC1
DDR_PGinB83.3VPower 7A SC1
DONEinG41.8VPS Config SC2
DP_AUX_DEoutAB133.3VDP SC1
DP_AUX_RXinAB123.3VDPSC1
DP_AUX_TXoutAA143.3VDP SC1
DP_ENoutM41.8VPower 8SC2
DP_TX_HPDinAA153.3VDP SC1
EN_12VoutC103.3VPower 1 SC1
EN_3.3V / EN_3P3VoutY83.3VPower 2 SC1
EN_A_3V3outY183.3VPower 8 FMCSC1
EN_AF_1V8outW193.3VPower 8 FMCSC1
EN_B_3V3outG113.3VPower 8 FMC SC1
EN_BC_1V8outA33.3VPower 8 FMCSC1
EN_C_3V3outE113.3VPower 8 FMCSC1
EN_D_3V3outF83.3VPower 8 FMCSC1
EN_DE_1V8outC53.3VPower 8 FMCSC1
EN_E_3V3outE83.3VPower 8 FMCSC1
EN_F_3V3outY103.3VPower 8 FMC SC1
EN_GT_LoutA73.3VPower 4B,CSC1
EN_GT_RoutB73.3VPower 4B,CSC1
EN_SFP_SSDoutW83.3VPower 8SC1
EN_VCCINToutB93.3VPower 1 SC1
ERR_OUTinH11.8VPS Config SC2
ERR_STATUSinJ21.8VPS Config  SC2
ETH_RSToutL61.8VReset SC2
F_LA06_SC_N
M19FMC_AF_1.8V / currently_not_usedSC2
F_LA06_SC_P
M18FMC_AF_1.8V / currently_not_usedSC2
F_LA07_SC_N
P21FMC_AF_1.8V / currently_not_usedSC2
F_LA07_SC_P
N20FMC_AF_1.8V / currently_not_usedSC2
F_LA08_SC_N
N18FMC_AF_1.8V / currently_not_usedSC2
F_LA08_SC_P
M20FMC_AF_1.8V / currently_not_usedSC2
F_LA09_SC_N
R18FMC_AF_1.8V / currently_not_usedSC2
F_LA09_SC_P
R19FMC_AF_1.8V / currently_not_usedSC2
F_LA10_SC_N
R20FMC_AF_1.8V / currently_not_usedSC2
F_LA10_SC_P
R21FMC_AF_1.8V / currently_not_usedSC2
F_LA11_SC_N
U19FMC_AF_1.8V / currently_not_usedSC2
F_LA11_SC_P
T19FMC_AF_1.8V / currently_not_usedSC2
F_LA12_SC_N
P18FMC_AF_1.8V / currently_not_usedSC2
F_LA12_SC_P
P19FMC_AF_1.8V / currently_not_usedSC2
F_LA13_SC_N
U17FMC_AF_1.8V / currently_not_usedSC2
F_LA13_SC_P
U18FMC_AF_1.8V / currently_not_usedSC2
F_LA14_SC_N
R17FMC_AF_1.8V / currently_not_usedSC2
F_LA14_SC_P
T18FMC_AF_1.8V / currently_not_usedSC2
F_LA15_SC_N
R16FMC_AF_1.8V / currently_not_usedSC2
F_LA15_SC_P
T17FMC_AF_1.8V / currently_not_usedSC2
F_LA16_SC_N
V19FMC_AF_1.8V / currently_not_usedSC2
F_LA16_SC_P
W20FMC_AF_1.8V / currently_not_usedSC2
F_LA17_SC_N
N16FMC_AF_1.8V / currently_not_usedSC2
F_LA17_SC_P
N17FMC_AF_1.8V / currently_not_usedSC2
F_LA18_SC_N
L16FMC_AF_1.8V / currently_not_usedSC2
F_LA18_SC_P
L17FMC_AF_1.8V / currently_not_usedSC2
F_LA19_SC_N
M16FMC_AF_1.8V / currently_not_usedSC2
F_LA19_SC_P
M17FMC_AF_1.8V / currently_not_usedSC2
F_LA20_SC_N
N6FMC_AF_1.8V / currently_not_usedSC2
F_LA20_SC_P
N7FMC_AF_1.8V / currently_not_usedSC2
F_LA21_SC_N
T6FMC_AF_1.8V / currently_not_usedSC2
F_LA21_SC_P
R7FMC_AF_1.8V / currently_not_usedSC2
F_LA22_SC_N
T5FMC_AF_1.8V / currently_not_usedSC2
F_LA22_SC_P
R6FMC_AF_1.8V / currently_not_usedSC2
F_LA23_SC_N
P6FMC_AF_1.8V / currently_not_usedSC2
F_LA23_SC_P
P7FMC_AF_1.8V / currently_not_usedSC2
F_LA24_SC_N
W3FMC_AF_1.8V / currently_not_usedSC2
F_LA24_SC_P
V4FMC_AF_1.8V / currently_not_usedSC2
F_LA25_SC_N
Y2FMC_AF_1.8V / currently_not_usedSC2
F_LA25_SC_P
W4FMC_AF_1.8V / currently_not_usedSC2
F_LA26_SC_N
U4FMC_AF_1.8V / currently_not_usedSC2
F_LA26_SC_P
T4FMC_AF_1.8V / currently_not_usedSC2
F_LA27_SC_N
U5FMC_AF_1.8V / currently_not_usedSC2
F_LA27_SC_P
T7FMC_AF_1.8V / currently_not_usedSC2
F_LA28_SC_N
V2FMC_AF_1.8V / currently_not_usedSC2
F_LA28_SC_P
W1FMC_AF_1.8V / currently_not_usedSC2
F_LA29_SC_N
AA1FMC_AF_1.8V / currently_not_usedSC2
F_LA29_SC_P
Y1FMC_AF_1.8V / currently_not_usedSC2
F_LA30_SC_N
V1FMC_AF_1.8V / currently_not_usedSC2
F_LA30_SC_P
U3FMC_AF_1.8V / currently_not_usedSC2
F_LA31_SC_N
V3FMC_AF_1.8V / currently_not_usedSC2
F_LA31_SC_P
W2FMC_AF_1.8V / currently_not_usedSC2
F_LA32_SC_N
M3FMC_AF_1.8V / currently_not_usedSC2
F_LA32_SC_P
N5FMC_AF_1.8V / currently_not_usedSC2
F_LA33_SC_N
R2FMC_AF_1.8V / currently_not_usedSC2
F_LA33_SC_P
R3FMC_AF_1.8V / currently_not_usedSC2
F1_ENoutC83.3VFAN SC1
F1PWMoutE103.3VFANSC1
F1SENSEinD113.3VFAN SC1
F2_ENoutB43.3VFANSC1
F2PWMoutD93.3VFANSC1
F2SENSEinG123.3VFANSC1
F3_ENoutA123.3VFANSC1
F3PWMoutB133.3VFANSC1
F3SENSEinA133.3VFANSC1
FAN_A_ENoutY193.3VFANSC1
FAN_B_ENoutA23.3VFAN SC1
FAN_C_ENoutB33.3VFANSC1
FAN_D_ENoutD73.3VFANSC1
FAN_E_ENoutD63.3VFANSC1
FAN_F_ENoutW183.3VFANSC1
FMC12V_ENoutAA83.3VPower 8 FMCSC1
FMCA_PG_C2MinoutE163.3VPower 8 FMCSC1
FMCA_PG_M2CinF173.3VPower 8 FMCSC1
FMCA_PRSNTinF163.3VPower 8 FMCSC1
FMCA_TCKoutT163.3VJTAGSC1
FMCA_TDIoutU153.3VJTAGSC1
FMCA_TDOinU163.3VJTAGSC1
FMCA_TMSoutV173.3VJTAGSC1
FMCAF_12V_PGinW93.3VPower 8 FMCSC1
FMCB_PG_C2MinoutC43.3VPower 8 FMCSC1
FMCB_PG_M2CinD53.3VPower 8 FMCSC1
FMCB_PRSNTinD43.3VPower 8 FMCSC1
FMCB_TCKoutE63.3VJTAG SC1
FMCB_TDIoutD83.3VJTAGSC1
FMCB_TDOinE93.3VJTAG SC1
FMCB_TMSoutF103.3VJTAGSC1
FMCC_PG_C2MinoutU63.3VPower 8 FMCSC1
FMCC_PG_M2CinV63.3VPower 8 FMC SC1
FMCC_PRSNTinW53.3VPower 8 FMCSC1
FMCC_TCKoutW63.3VJTAGSC1
FMCC_TDIoutY43.3VJTAGSC1
FMCC_TDOinY53.3VJTAGSC1
FMCC_TMSoutAA33.3VJTAGSC1
FMCD_PG_C2MinoutG83.3VPower 8 FMCSC1
FMCD_PG_M2CinG103.3VPower 8 FMC SC1
FMCD_PRSNTinAA43.3VPower 8 FMCSC1
FMCD_TCKoutT123.3VJTAGSC1
FMCD_TDIoutU83.3VJTAGSC1
FMCD_TDOinV93.3VJTAGSC1
FMCD_TMSoutU103.3VJTAGSC1
FMCE_PG_C2MinoutAB33.3VPower 8 FMC SC1
FMCE_PG_M2CinAB23.3VPower 8 FMC SC1
FMCE_PRSNTinAB53.3VPower 8 FMCSC1
FMCE_TCKoutY63.3VJTAGSC1
FMCE_TDIoutAB63.3VJTAGSC1
FMCE_TDOinAA73.3VJTAGSC1
FMCE_TMSoutAB73.3VJTAGSC1
FMCF_PG_C2MinoutAB203.3VPower 8 FMC SC1
FMCF_PG_M2CinAB213.3VPower 8 FMCSC1
FMCF_PRSNTinAA193.3VPower 8 FMCSC1
FMCF_TCKoutW113.3VJTAGSC1
FMCF_TDIoutV113.3VJTAGSC1
FMCF_TDOinAB103.3VJTAGSC1
FMCF_TMSoutAA103.3VJTAGSC1
I2C_RSToutL21.8VResetSC2
INIT_BinJ31.8VPS ConfigSC2
JTAGENBinA163.3VJTAG /  Enable to get access to CPLD over JTAG. Pin is not accessible on CPLD. Is set by DIP-Switch S3-2SC1
LED_1AoutY123.3VETH LED yellow (right connector LED)SC1
LED_2AoutY133.3VETH LED green (left connector LED) (LED_2A high LED_2B low)SC1
LED_2BoutY143.3VETH LED orange (left connector LED) (LED_2B high LED_2A low)SC1
LED1outU123.3VUSR (D13 green) SC1
LED2outV123.3VUSR (D14 green) SC1
LED3outW123.3VUSR (D15 green) SC1
LED4outV133.3VUSR (D16 red)SC1
MEM_SCLinW163.3VI2CSC1
MEM_SDAinoutV163.3VI2CSC1
MIO24
F51.8VMIO  / currently_not_usedSC2
MIO25
G51.8VMIO  / currently_not_usedSC2
MIO26outG153.3VMIO / PJTAG TCKSC1
MIO27outE123.3VMIO / PJTAG TDISC1
MIO28inE153.3VMIO / PJTAG TDOSC1
MIO29outC113.3VMIO / PJTAG TMSSC1
MIO30outC133.3VMIO / Status LEDSC1
MIO31inB123.3VMIO  / currently_not_usedSC1
MIO32
B113.3VMIO  / currently_not_usedSC1
MIO33inU73.3VMIO / PCIe ResetSC1
MIO34outD123.3VMIO / CAN
SC1
MIO35inF153.3VMIO  / CANSC1
MIO36
G73.3VMIO  / currently_not_usedSC1
MIO37
D143.3VMIO  / currently_not_usedSC1
MIO40
F123.3VMIO  / currently_not_usedSC1
MIO41
T83.3VMIO  / currently_not_usedSC1
MIO42outB143.3VMIO / UART RXSC1
MIO43inE73.3VMIO / UART TXSC1
MIO44outE143.3VMIO / SD-WPSC1
MIO45outA203.3VMIO / SD-CPSC1
MIO6inF61.8VMIO / QSPI FB CLK from ZynqMPSC2
MODE0outH31.8VPS Config Boot Mode SC2
MODE1outH21.8VPS Config Boot Mode SC2
MODE2outG21.8VPS Config Boot Mode SC2
MODE3outG11.8VPS Config  Boot Mode SC2
MRoutL71.8VPS Config (PS_POR_B)  ResetSC2
NCoutAA203.3Vused as dummi output pin / Not connectedSC1
NC
T153.3VNot connectedSC1
NC
V153.3VNot connectedSC1
NC
W153.3VNot connectedSC1
NC
V143.3VNot connectedSC1
NC
W143.3VNot connectedSC1
NC
U133.3VNot connectedSC1
NC
T133.3VNot connectedSC1
NC
AB163.3VNot connectedSC1
NC
Y33.3VNot connectedSC1
NC
A213.3VNot connectedSC1
NC
G61.8VNot connectedSC2
NC
N11.8VNot connectedSC2
NC
N21.8VNot connectedSC2
NC
M11.8VNot connectedSC2
NC
N31.8VNot connectedSC2
NC
P21.8VNot connectedSC2
NC
M71.8VNot connectedSC2
NC
M61.8VNot connectedSC2
NC
P31.8VNot connectedSC2
NC
R11.8VNot connectedSC2
NC
M51.8VNot connectedSC2
NC
H51.8VNot connectedSC2
NC
J51.8VNot connectedSC2
NC
J41.8VNot connectedSC2
NC
K51.8VNot connectedSC2
NC
L31.8VNot connectedSC2
PG_12VinA113.3VPower 1 SC1
PG_FPDinA103.3VPower 2SC1
PG_GT_LinK31.8VPower 5BCSC2
PG_GT_RinF113.3VPower 5BCSC1
PG_PSGTinA53.3VPower 6A SC1
PHY_CLK125MinK21.8VCLKSC2
PHY_LED0inL51.8VPHY LEDSC2
PHY_LED1inL11.8VPHY LEDSC2
PHY_LED2inK11.8V / currently_not_usedSC2
PLL_RSToutL41.8VReset SC2
PROG_BoutE21.8V PS Config (opt. PL Reset)SC2
PSGT_ENoutB103.3VPower 4ASC1
SC_SW1inE173.3VUSR S3-3 / Set Boot ModeSC1
SC_SW2inD163.3VUSR S3-4 / Set Boot Mode SC1
SD_CDinT113.3VSD CDSC1
SD_ENoutU113.3VPower 8SC1
SD_WPinT103.3VSD WPSC1
SFP_LED1
AB173.3V / currently_not_usedSC1
SFP_LED2
AB183.3V / currently_not_usedSC1
SFP_LED3
AA163.3V / currently_not_usedSC1
SFP_LED4
AB153.3V / currently_not_usedSC1
SFP0_LOS
V83.3V / currently_not_usedSC1
SFP0_TX_DISoutY73.3VSFPSC1
SFP1_LOS
W73.3V / currently_not_usedSC1
SFP1_TX_DIS
V73.3VSFPSC1
SI5345_CLK
E11.8V / currently_not_usedSC2
SSD1_LED
AA133.3V / currently_not_usedSC1
SSD1_PERSTNoutAA113.3VSSD Reset SC1
SSD1_SLEEP
AA123.3V / currently_not_usedSC1
SSD1_WAKEoutAB113.3VSSDSC1
U_SW1inD183.3VUSR (S4-1) / currently_not_usedSC1
U_SW2inD173.3VUSR (S4-2) / currently_not_usedSC1
U_SW3inC193.3VUSR (S4-3)/ currently_not_usedSC1
U_SW4inC183.3VUSR (S4-4) / currently_not_usedSC1
USB0_RSToutM21.8VReset SC2
USBH_MODE0outY173.3VUSBSC1
USBH_MODE1outY163.3VUSBSC1
USBH_RSToutY153.3VReset SC1
USR_BUT1inF133.3VUSR (S1)  SC1
USR_BUT2inG133.3VUSR (S2) / Power Reset SC1
USR_BUT3inW173.3VUSR (S3) / optional Power Reset SC1N.C. on PCB REV02,REV03
XMOD1_A
B193.3VXMOD J35 / currently_not_usedSC1
XMOD1_BoutA173.3VXMOD J35 LED / Attention this is connected to XMOD1_E SC1
XMOD1_E
C173.3VXMOD J35 / Attention this is connected to XMOD1_B  / currently_not_usedSC1
XMOD1_GinA183.3VXMOD  J35 Button  SC1
XMOD2_AoutK71.8VUART RXD (XMOD J24) SC2
XMOD2_BinK61.8VUART TX  (XMOD J24) SC2
XMOD2_EoutH71.8VXMOD J24 LED / Boot ModeSC2
XMOD2_GinH61.8VXMOD J24 Button / PS Reset SC2


Functional Description

JTAG

JTAG access over CPLD XMOD J35.

Set DIP-Switch S3-2 to ON to get CPLD into JTAG Chain. This is only needed for CPLD update. Otherwise JTAG is routed thought FMCs or to PJTAG dependign on boot mode. JTAG is connected into cascade from FMC A to F, if module is detected, otherwise corresponding connector is left out.

Boot ModeDescription
PJTAG0PJTAG MIOs are connected to JTAG chain
all otherFMC IOs are connected to JTAG chain

Note: FPGA/SoC JTAG access is available directly over second XMOD.

Power

Power is controlled by different state machines and can be restart over S2 Button or S3 Button (PCB REV04 only). Main Power sequence must be finished successfully before other power management units starts. Power Management can be checked over status LEDs, see LED section.

Main Power:

StateConditions for next stateDescription
1:IDLEPG_12V is ready

Start with this state on power up or Power Reset

  • EN12V is enabled, EN_VCCINT, EN_3P3V, DDR_EN are disabled
2:PER1_ENPG_FPD is ready
  • EN12V, EN_VCCINT, EN_3P3V are enabled, DDR_EN is is disabled
3:PER2_ENDDR_PG is ready
  • EN12V, EN_VCCINT, EN_3P3V DDR_EN are enabled 
4:RDYDDR_PG or PG_FPD or PG_12V failedNormal state if power sequence was ok.
5:ERROR---Only set, if a error occurs after successfully power up. Manually reset is needed.

MGT Power:

StateConditions for next stateDescription
1:IDLEMain Power sequence is done

Start with this state if main power is stared.

  • PSGT_EN, EN_GT_L, EN_GT_R are disabled
2:PER1_ENPG_PSGT, PG_GT_L, PG_GT_R are ready
  • SGT_EN, EN_GT_L, EN_GT_R are enabled
3:RDYPG_PSGT or  PG_GT_L or  PG_GT_R failedNormal state if power sequence was ok.
4:ERROR---Only set if a error occurs after successfully power up. Manually reset is needed.

Periphery Power:

StateConditions for next stateDescription
1:IDLEMain Power sequence is done

Start with this state if main power is stared.

  • DP_EN, EN_SFP_SSD, SD_EN are disabled
2:PER1_ENNo check possible, next state is RDY
  • DP_EN, EN_SFP_SSD, SD_EN are enabled
3:RDYNo check possibleNormal state if power sequence was ok.
4:ERROR---This state should never occurs.

FMC A and F Power:

StateConditions for next stateDescription
1:IDLEMain Power sequence is done

Start with this state if main power is stared.

  • FMC12V_EN, EN_AF_1V8, EN_A_3V3, EN_F_3V3, FMCF_PG_C2M, FMCA_PG_C2M are disabled
2:PER1_ENFMCAF_12V_PG, FMCF_PG_C2M, FMCA_PG_C2M are ready
  • FMC12V_EN, EN_AF_1V8, EN_A_3V3, EN_F_3V3, FMCF_PG_C2M, FMCA_PG_C2M are enabled
3:RDYFMCAF_12V_PG or FMCF_PG_C2M or FMCA_PG_C2M failedNormal state if power sequence was ok.
4:ERROR---Only set if a error occurs after successfully power up. Manually reset is needed.

* FMCF_PG_C2M, FMCA_PG_C2M are bidirectional.  External Pull up is used to check power fails.

FMC B,C,D,E Power:

StateConditions for next stateDescription
1:IDLEMain Power sequence is done

Start with this state if main power is stared.

  • EN_BC_1V8, EN_DE_1V8, EN_B_3V3, EN_C_3V3, EN_D_3V3, EN_E_3V3, FMCB_PG_C2M, FMCC_PG_C2M, FMCD_PG_C2M, FMCE_PG_C2M are disabled
2:PER1_ENFMCB_PG_C2M, FMCC_PG_C2M, FMCD_PG_C2M, FMCE_PG_C2M are ready
  • EN_BC_1V8, EN_DE_1V8, EN_B_3V3, EN_C_3V3, EN_D_3V3, EN_E_3V3, FMCB_PG_C2M, FMCC_PG_C2M, FMCD_PG_C2M, FMCE_PG_C2M are enabled

3:RDYFMCB_PG_C2M or FMCC_PG_C2M or FMCD_PG_C2M or FMCE_PG_C2M failedNormal state if power sequence was ok.
4:ERROR---Only set if a error occurs after successfully power up. Manually reset is needed.

FMCF_PB_C2M, FMCC_PG_C2M, FMCD_PG_C2M, FMCE_PG_C2M are bidirectional.  External Pull up is used to check power fails. 12V is sourced  and controlled by main power.


Reset

ButtonDescription
S2Main Power Reset Button. Restart power management.
FPGA XMODPS MR  Reset Button. Restart PS (PS_POR_B)
  • Buttons are debounced.

For all other resets, see component sections.

Boot Mode

S3-3 (SC_SW1)S3-4 (SC_SW2)Description
OFFOFFSD1 Boot Mode (SD-Card on J11), if SD is insered
OFFOFFeMMC Boot Mode, if SD is not insered
OFFONPJTAG0
ONOFFQSPI32
ONONJTAG


Display Port

OutputInput
DP_AUX_TXB66_T1
DP_AUX_DEnot B66_T2
B66_T3DP_AUX_RX
B67_T1DP_TX_HPD

CAN

  • CAN_S soured by B65_T1
  • CAN_FAULT is connected to B65_T2
  • CAN_RX is connected to MIO34
  • CAN_TX  sourced by MIO35

SD

  • SD_EN is controlled by power management.
  • SD_CD is connected to MIO45.
  • SD_WP is connected to MIO44.

SFP

  • Transmit for all SFP is enabled.

USB

  • USB Mode pins constant "11" (default boot mode).
  • USB0_RST is controlled by power management.
  • USBH_RST is controlled by power management.

SSD

  • SSD1_WAKE is "0".
  • SSD1_PERSTn is controlled by power management and MIO33.

I2C

  • I2C_RST is controlled by power management.

FAN

FAN1 to FAN3 speed can be controlled via I2C Bus. FMC FANs can be disabled over I2C Bus and only run, if FMCx_PRESNT is available.

I2C Baseaddress: 0x74. I2C with 8Bit Register Address with 8Bit Data. I2C CLK currently 100 MHz supported.

Write Access:

Register AddressNameDescription
0FAN CTRL

Enable FAN, Bit 0-2 Fan1 to Fan2, Bit 3 FMC B, Bit 4 FMC C , Bit 5 FMC D , Bit 6 FMC E, Bit 7 FMC A and F. Default all enabled (1)

1FAN1 PWMFAN1 PWM (0%-100%, Default 30%)
2FAN2 PWMFAN2 PWM (0%-100%, Default 30%)
3FAN3 PWMFAN3 PWM (0%-100%, Default 30%)

Read Access:

Register AddressNameDescription
0FAN CTRLFAN Control register
1FAN1 RPSFAN1 Revolutions per second
2FAN2 RPSFAN2 Revolutions per second
3FAN3 RPSFAN3 Revolutions per second


FMC

FMC present (FMCx_PRESNT) signals are used for board detect and enables.

FMC JTAG: See JTAG section

FAN : See FAN section


UART

UART is connected to FPGA XMOOD on J24. XMOD UART RXD output is connected to MIO42. MIO43 is connected to XMOD UART TX input.

USR Buttons and Switches

---

LED

LEDDescription
LED4 (D16 red)

User FPGA IO B67_T3

LED3 (D15 green)User FPGA IO B67_T2
LED2 (D14 green)

PS Status. Status depends on blink sequence and priority.

  1. ********    : Reset button is pressed
  2. *****ooo   : Init_B failed
  3. ****oooo   : PS_Error_Status and PS_Error failed
  4. ***ooooo   : PS_Error_Status failed
  5. **oooooo  : PS_Error failed
  6. *ooooooo  : Done is low-> SoC PL not programmed
  7. LED OFF or ON :  user defined from MIO30
LED4 (D13 green)Power LED. Status depends on blink sequence and priority.
  1. LED OFF: Power button is pressed (Note, 1 and 8 are swapped with CPLD REV03)
  2. ********    : Main power up failed
  3. *****ooo   : Main power error after successfully startup
  4. *****ooo   : MGT or Periphery power up failed
  5. ***ooooo  : MGT or Periphery power error after successfully startup
  6. **oooooo  : FMC power up failed
  7. *ooooooo : FMC power error after successfully startup
  8. LED ON: Power good (Note, 1 and 8 are swapped with CPLD REV03)
FPGA XMOD (J24-XMOD2)

Boot Mode. Status depends on blink sequence and priority.

  1. LED ON  : JTAG
  2. ********    : Error unknown state
  3. *****ooo   : not used
  4. *****ooo   : not used
  5. ***ooooo  : not used
  6. **oooooo  : QSPI
  7. *ooooooo : PJTAG_0
  8. LED OFF : SD1
CPLD XMOD (J35-XMOD1)
  1. ********    : one or more of FMCx_PG_M2C of connected FMC are not ready
  2. LED OFF : all connected FMCx_PG_M2C are ready
ETH LED Left (Green/Orange)

OFF, if Main Power Failed otherwise PHY_LED0(depends on PHY Configuration)

  • Green, if FAN1...3 enabled and FMC FAN with connected modules are enabled
  • Orange, if one of FAN1..3 or FMC FAN wirg connected modules are disabled
ETH LED Right (Yellow)OFF, if Main Power Failed otherwise PHY_LED1(depends on PHY Configuration)


Appx. A: Change History and Legal Notices

Revision Changes

CPLD REV04 to REV05

  • add can

  • DP_TX_HPD input pin threshold changed

CPLD REV03 to REV04

  • bugfix FMC JTAG (support multiple device in the chain now)

CPLD REV02 to REV03

  • add main Reset to optional User Button 3 (only on PCB REV04 usable)
  • add PHY LEDs
  • add emmC Boot Mode
  • new I2C controller
  • swapped LED1 0,7 state (LED ON is ready now)

CPLD REV01 to REV02

  • Correction of FAN_A_EN and FAN_AF_EN Location constrains

  • Add Pullup attribute to FMCX_PRSNT signals

  • I2C Enable mapping is changed

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

REV05REV02, REV03, REV04
  • firmware update
  • released at 2019-09-10
2018-12-10v.29REV04REV02, REV03, REV04John Hartfiel
  • firmware update
  • released at 2018-12-06

2018-11-19

v.28REV03REV02, REV03, REV04John Hartfiel
  • firmware update
  • released at 2018-11-19

2018-02-02

v.24REV02REV02, REV03John Hartfiel
  • add PCB REV03 support
2017-09-18v.23REV02REV02John Hartfiel
  • Revision 02 finished
2017-08-16v.21REV01REV02John Hartfiel
  • Revision 01 finished
2017-07-25v.1REV01REV02
  • Initial release

All


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Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

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WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

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