Overview

Firmware for PCB CPLD with designator U27. CPLD Device in Chain: LCMX02-7000HC

Feature Summary

  • Power Management
  • Reset Management
  • Boot Mode Selection
  • FAN Control over I2C (via emc230x emulator IP)
  • LED Control
  • CPLD Status Information over I2C
  • Diverse Signals routing: CAN, SD, SFP. USB, SSD, FMC JTAG, PJTAG

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinPullup/PulldownBank PowerDescriptionSchematic SheetPCB < REV05PCB < REV03
FMCE_PWMoutB16none3.3VPWM output / CPLD Programm Pin connected with pullupSC1ext. pullup only
FMCC_PWMoutB20none3.3VPWM output / CPLD initn Pin connected with pullupSC1ext. pullup only
FMCD_PWMoutC20none3.3VPWM output / CPLD Done Pin connected with pullupSC1ext. pullup only
A_LA06_SC_N
C22
FMC_AF_1.8V / currently_not_usedSC2

A_LA06_SC_P
B22
FMC_AF_1.8V / currently_not_usedSC2

A_LA07_SC_N
F20
FMC_AF_1.8V / currently_not_usedSC2

A_LA07_SC_P
E22
FMC_AF_1.8V / currently_not_usedSC2

A_LA08_SC_N
E21
FMC_AF_1.8V / currently_not_usedSC2

A_LA08_SC_P
D22
FMC_AF_1.8V / currently_not_usedSC2

A_LA09_SC_N
G22
FMC_AF_1.8V / currently_not_usedSC2

A_LA09_SC_P
G21
FMC_AF_1.8V / currently_not_usedSC2

A_LA10_SC_N
G17
FMC_AF_1.8V / currently_not_usedSC2

A_LA10_SC_P
H16
FMC_AF_1.8V / currently_not_usedSC2

A_LA11_SC_N
K22
FMC_AF_1.8V / currently_not_usedSC2

A_LA11_SC_P
K21
FMC_AF_1.8V / currently_not_usedSC2

A_LA12_SC_N
H20
FMC_AF_1.8V / currently_not_usedSC2

A_LA12_SC_P
H21
FMC_AF_1.8V / currently_not_usedSC2

A_LA13_SC_N
L22
FMC_AF_1.8V / currently_not_usedSC2

A_LA13_SC_P
L21
FMC_AF_1.8V / currently_not_usedSC2

A_LA14_SC_N
G16
FMC_AF_1.8V / currently_not_usedSC2

A_LA14_SC_P
F18
FMC_AF_1.8V / currently_not_usedSC2

A_LA15_SC_N
D19
FMC_AF_1.8V / currently_not_usedSC2

A_LA15_SC_P
C21
FMC_AF_1.8V / currently_not_usedSC2

A_LA16_SC_N
M21
FMC_AF_1.8V / currently_not_usedSC2

A_LA16_SC_P
M22
FMC_AF_1.8V / currently_not_usedSC2

A_LA17_SC_N
N21
FMC_AF_1.8V / currently_not_usedSC2

A_LA17_SC_P
N22
FMC_AF_1.8V / currently_not_usedSC2

A_LA18_SC_N
G19
FMC_AF_1.8V / currently_not_usedSC2

A_LA18_SC_P
F19
FMC_AF_1.8V / currently_not_usedSC2

A_LA19_SC_N
E19
FMC_AF_1.8V / currently_not_usedSC2

A_LA19_SC_P
D20
FMC_AF_1.8V / currently_not_usedSC2

A_LA20_SC_N
E20
FMC_AF_1.8V / currently_not_usedSC2

A_LA20_SC_P
D21
FMC_AF_1.8V / currently_not_usedSC2

A_LA21_SC_N
J17
FMC_AF_1.8V / currently_not_usedSC2

A_LA21_SC_P
J16
FMC_AF_1.8V / currently_not_usedSC2

A_LA22_SC_N
J19
FMC_AF_1.8V / currently_not_usedSC2

A_LA22_SC_P
J18
FMC_AF_1.8V / currently_not_usedSC2

A_LA23_SC_N
G18
FMC_AF_1.8V / currently_not_usedSC2

A_LA23_SC_P
H17
FMC_AF_1.8V / currently_not_usedSC2

A_LA24_SC_N
R22
FMC_AF_1.8V / currently_not_usedSC2

A_LA24_SC_P
P20
FMC_AF_1.8V / currently_not_usedSC2

A_LA25_SC_N
K16
FMC_AF_1.8V / currently_not_usedSC2

A_LA25_SC_P
K17
FMC_AF_1.8V / currently_not_usedSC2

A_LA26_SC_N
K18
FMC_AF_1.8V / currently_not_usedSC2

A_LA26_SC_P
L20
FMC_AF_1.8V / currently_not_usedSC2

A_LA27_SC_N
K20
FMC_AF_1.8V / currently_not_usedSC2

A_LA27_SC_P
J21
FMC_AF_1.8V / currently_not_usedSC2

A_LA28_SC_N
U22
FMC_AF_1.8V / currently_not_usedSC2

A_LA28_SC_P
T20
FMC_AF_1.8V / currently_not_usedSC2

A_LA29_SC_N
T22
FMC_AF_1.8V / currently_not_usedSC2

A_LA29_SC_P
T21
FMC_AF_1.8V / currently_not_usedSC2

A_LA30_SC_N
W22
FMC_AF_1.8V / currently_not_usedSC2

A_LA30_SC_P
V21
FMC_AF_1.8V / currently_not_usedSC2

A_LA31_SC_N
V22
FMC_AF_1.8V / currently_not_usedSC2

A_LA31_SC_P
U20
FMC_AF_1.8V / currently_not_usedSC2

A_LA32_SC_N
Y20
FMC_AF_1.8V / currently_not_usedSC2

A_LA32_SC_P
Y21
FMC_AF_1.8V / currently_not_usedSC2

A_LA33_SC_N
AA22
FMC_AF_1.8V / currently_not_usedSC2

A_LA33_SC_P
Y22
FMC_AF_1.8V / currently_not_usedSC2

B64_T1
D3
1.8V/ currently_not_implementedSC2

B64_T2
C3
1.8V/ currently_not_implementedSC2

B64_T3
B1
1.8V/ currently_not_implementedSC2

B65_T1inC2down1.8VCAN_S (with pulldown)SC2

B65_T2outE4none1.8VCAN_FAULTSC2

B65_T3
C1
1.8V / currently_not_usedSC2

B66_T1inD1none1.8VFPGA / dp_aux_data_outSC2

B66_T2inF4none1.8VFPGA / dp_aux_data_oe_nSC2

B66_T3outF3none1.8VFPGA / dp_aux_data_SC2

B67_T1outF1none1.8VFPGA / dp_hot_plug_detectSC2

B67_T2inG3
1.8VFPGA /  LED SC2

B67_T3inH4
1.8VFPGA / LED SC2

C_TCKinA8none3.3VJTAG  CPLD XMODSC1

C_TDIinC7up3.3V

JTAG CPLD XMOD

 
SC1

C_TDOoutA6none3.3VJTAG CPLD XMODSC1

C_TMSinC9none3.3VJTAG CPLD XMODSC1

CAN_FAULTinD15up3.3VCAN / B65_T2SC1

CAN_RXinB15none3.3VCAN / MIO34SC1

CAN_SoutC15none3.3VCAN /  B65_T1SC1

CAN_TXoutC16none3.3VCAN / MIO35SC1

CLK_SCinAA9
3.3Vexternal User CLK 25MHz (oscillator is assembly option)  / currently_not_usedSC1

DDR_ENoutC6none3.3VPower 7ASC1

PG_DDR_1V2inB8up3.3VPower 7A SC1DDR_PG (renamed)
DONEinG4none1.8VPS Config SC2

DP_AUX_DEoutAB13none3.3VDP SC1

DP_AUX_RXinAB12none3.3VDPSC1

DP_AUX_TXoutAA14none3.3VDP SC1

DP_ENoutM4none1.8VPower 8SC2

DP_TX_HPDinAA15none3.3VDP SC1

EN_12VoutC10none3.3VPower 1 SC1

EN_3.3V / EN_3P3VoutY8none3.3VPower 2 SC1

EN_A_3V3outY18none3.3VPower 8 FMCSC1

EN_AF_1V8outW19none3.3VPower 8 FMCSC1

EN_B_3V3outG11none3.3VPower 8 FMC SC1

EN_BC_1V8outA3none3.3VPower 8 FMCSC1

EN_C_3V3outE11none3.3VPower 8 FMCSC1

EN_D_3V3outF8none3.3VPower 8 FMCSC1

EN_DE_1V8outC5none3.3VPower 8 FMCSC1

EN_E_3V3outE8none3.3VPower 8 FMCSC1

EN_F_3V3outY10none3.3VPower 8 FMC SC1

EN_GT_LoutA7none3.3VPower 4B,CSC1

EN_GT_RoutB7none3.3VPower 4B,CSC1

EN_SFP_SSDoutW8none3.3VPower 8SC1

EN_VCCINToutB9none3.3VPower 1 SC1

ERR_OUTinH1none1.8VPS Config SC2

ERR_STATUSinJ2none1.8VPS Config  SC2

ETH_RSToutL6none1.8VReset SC2

F_LA06_SC_N
M19
FMC_AF_1.8V / currently_not_usedSC2

F_LA06_SC_P
M18
FMC_AF_1.8V / currently_not_usedSC2

F_LA07_SC_N
P21
FMC_AF_1.8V / currently_not_usedSC2

F_LA07_SC_P
N20
FMC_AF_1.8V / currently_not_usedSC2

F_LA08_SC_N
N18
FMC_AF_1.8V / currently_not_usedSC2

F_LA08_SC_P
M20
FMC_AF_1.8V / currently_not_usedSC2

F_LA09_SC_N
R18
FMC_AF_1.8V / currently_not_usedSC2

F_LA09_SC_P
R19
FMC_AF_1.8V / currently_not_usedSC2

F_LA10_SC_N
R20
FMC_AF_1.8V / currently_not_usedSC2

F_LA10_SC_P
R21
FMC_AF_1.8V / currently_not_usedSC2

F_LA11_SC_N
U19
FMC_AF_1.8V / currently_not_usedSC2

F_LA11_SC_P
T19
FMC_AF_1.8V / currently_not_usedSC2

F_LA12_SC_N
P18
FMC_AF_1.8V / currently_not_usedSC2

F_LA12_SC_P
P19
FMC_AF_1.8V / currently_not_usedSC2

F_LA13_SC_N
U17
FMC_AF_1.8V / currently_not_usedSC2

F_LA13_SC_P
U18
FMC_AF_1.8V / currently_not_usedSC2

F_LA14_SC_N
R17
FMC_AF_1.8V / currently_not_usedSC2

F_LA14_SC_P
T18
FMC_AF_1.8V / currently_not_usedSC2

F_LA15_SC_N
R16
FMC_AF_1.8V / currently_not_usedSC2

F_LA15_SC_P
T17
FMC_AF_1.8V / currently_not_usedSC2

F_LA16_SC_N
V19
FMC_AF_1.8V / currently_not_usedSC2

F_LA16_SC_P
W20
FMC_AF_1.8V / currently_not_usedSC2

F_LA17_SC_N
N16
FMC_AF_1.8V / currently_not_usedSC2

F_LA17_SC_P
N17
FMC_AF_1.8V / currently_not_usedSC2

F_LA18_SC_N
L16
FMC_AF_1.8V / currently_not_usedSC2

F_LA18_SC_P
L17
FMC_AF_1.8V / currently_not_usedSC2

F_LA19_SC_N
M16
FMC_AF_1.8V / currently_not_usedSC2

F_LA19_SC_P
M17
FMC_AF_1.8V / currently_not_usedSC2

F_LA20_SC_N
N6
FMC_AF_1.8V / currently_not_usedSC2

F_LA20_SC_P
N7
FMC_AF_1.8V / currently_not_usedSC2

F_LA21_SC_N
T6
FMC_AF_1.8V / currently_not_usedSC2

F_LA21_SC_P
R7
FMC_AF_1.8V / currently_not_usedSC2

F_LA22_SC_N
T5
FMC_AF_1.8V / currently_not_usedSC2

F_LA22_SC_P
R6
FMC_AF_1.8V / currently_not_usedSC2

F_LA23_SC_N
P6
FMC_AF_1.8V / currently_not_usedSC2

F_LA23_SC_P
P7
FMC_AF_1.8V / currently_not_usedSC2

F_LA24_SC_N
W3
FMC_AF_1.8V / currently_not_usedSC2

F_LA24_SC_P
V4
FMC_AF_1.8V / currently_not_usedSC2

F_LA25_SC_N
Y2
FMC_AF_1.8V / currently_not_usedSC2

F_LA25_SC_P
W4
FMC_AF_1.8V / currently_not_usedSC2

F_LA26_SC_N
U4
FMC_AF_1.8V / currently_not_usedSC2

F_LA26_SC_P
T4
FMC_AF_1.8V / currently_not_usedSC2

F_LA27_SC_N
U5
FMC_AF_1.8V / currently_not_usedSC2

F_LA27_SC_P
T7
FMC_AF_1.8V / currently_not_usedSC2

F_LA28_SC_N
V2
FMC_AF_1.8V / currently_not_usedSC2

F_LA28_SC_P
W1
FMC_AF_1.8V / currently_not_usedSC2

F_LA29_SC_N
AA1
FMC_AF_1.8V / currently_not_usedSC2

F_LA29_SC_P
Y1
FMC_AF_1.8V / currently_not_usedSC2

F_LA30_SC_N
V1
FMC_AF_1.8V / currently_not_usedSC2

F_LA30_SC_P
U3
FMC_AF_1.8V / currently_not_usedSC2

F_LA31_SC_N
V3
FMC_AF_1.8V / currently_not_usedSC2

F_LA31_SC_P
W2
FMC_AF_1.8V / currently_not_usedSC2

F_LA32_SC_N
M3
FMC_AF_1.8V / currently_not_usedSC2

F_LA32_SC_P
N5
FMC_AF_1.8V / currently_not_usedSC2

F_LA33_SC_N
R2
FMC_AF_1.8V / currently_not_usedSC2

F_LA33_SC_P
R3
FMC_AF_1.8V / currently_not_usedSC2

F1_ENoutC8none3.3VFAN SC1

F1PWMoutE10none3.3VFANSC1

F1SENSE / F1_SENSEinD11none3.3VFAN SC1

F2_ENoutB4none3.3VFANSC1

F2PWMoutD9none3.3VFANSC1

F2SENSE / F2_SENSEinG12none3.3VFANSC1

F3_ENoutA12none3.3VFANSC1

F3PWMoutB13none3.3VFANSC1

F3SENSE / F3_SENSEinA13none3.3VFANSC1

FAN_A_ENoutY19none3.3VFANSC1

FAN_B_ENoutA2none3.3VFAN SC1

FAN_C_ENoutB3none3.3VFANSC1

FAN_D_ENoutD7none3.3VFANSC1

FAN_E_ENoutD6none3.3VFANSC1

FAN_F_ENoutW18none3.3VFANSC1

FMC12V_ENoutAA8none3.3VPower 8 FMCSC1

SC_A_PG_C2MoutE16none3.3VPower 8 FMCSC1FMCA_PG_C2M
FMCA_PG_M2CinF17none3.3VPower 8 FMCSC1

FMCA_PRSNTinF16up3.3VPower 8 FMCSC1

FMCA_TCKoutT16none3.3VJTAGSC1

FMCA_TDIoutU15none3.3VJTAGSC1

FMCA_TDOinU16up3.3VJTAGSC1

FMCA_TMSoutV17none3.3VJTAGSC1

FMCAF_12V_PGinW9up3.3VPower 8 FMCSC1

SC_B_PG_C2MoutC4none3.3VPower 8 FMCSC1FMCB_PG_C2M
FMCB_PG_M2CinD5none3.3VPower 8 FMCSC1

FMCB_PRSNTinD4up3.3VPower 8 FMCSC1

FMCB_TCKoutE6none3.3VJTAG SC1

FMCB_TDIoutD8none3.3VJTAGSC1

FMCB_TDOinE9up3.3VJTAG SC1

FMCB_TMSoutF10none3.3VJTAGSC1

SC_C_PG_C2MoutU6none3.3VPower 8 FMCSC1FMCC_PG_C2M
FMCC_PG_M2CinV6none3.3VPower 8 FMC SC1

FMCC_PRSNTinW5up3.3VPower 8 FMCSC1

FMCC_TCKoutW6none3.3VJTAGSC1

FMCC_TDIoutY4none3.3VJTAGSC1

FMCC_TDOinY5up3.3VJTAGSC1

FMCC_TMSoutAA3none3.3VJTAGSC1

SC_D_PG_C2MoutG8none3.3VPower 8 FMCSC1FMCD_PG_C2M
FMCD_PG_M2CinG10none3.3VPower 8 FMC SC1

FMCD_PRSNTinAA4up3.3VPower 8 FMCSC1

FMCD_TCKoutT12none3.3VJTAGSC1

FMCD_TDIoutU8none3.3VJTAGSC1

FMCD_TDOinV9up3.3VJTAGSC1

FMCD_TMSoutU10none3.3VJTAGSC1

SC_E_PG_C2MoutAB3none3.3VPower 8 FMC SC1FMCE_PG_C2M
FMCE_PG_M2CinAB2none3.3VPower 8 FMC SC1

FMCE_PRSNTinAB5up3.3VPower 8 FMCSC1

FMCE_TCKoutY6none3.3VJTAGSC1

FMCE_TDIoutAB6none3.3VJTAGSC1

FMCE_TDOinAA7up3.3VJTAGSC1

FMCE_TMSoutAB7none3.3VJTAGSC1

SC_F_PG_C2MoutAB20none3.3VPower 8 FMC SC1FMCF_PG_C2M
FMCF_PG_M2CinAB21none3.3VPower 8 FMCSC1

FMCF_PRSNTinAA19up3.3VPower 8 FMCSC1

FMCF_TCKoutW11none3.3VJTAGSC1

FMCF_TDIoutV11none3.3VJTAGSC1

FMCF_TDOinAB10up3.3VJTAGSC1

FMCF_TMSoutAA10none3.3VJTAGSC1

I2C_RSToutL2none1.8VResetSC2

INIT_BinJ3up1.8VPS ConfigSC2

JTAGENBinA16
3.3VJTAG /  Enable to get access to CPLD over JTAG. Pin is not accessible on CPLD. Is set by DIP-Switch S3-2SC1

LED_1AoutY12none3.3VETH LED yellow (right connector LED)SC1

LED_2AoutY13none3.3VETH LED green (left connector LED) (LED_2A high LED_2B low)SC1

LED_2BoutY14none3.3VETH LED orange (left connector LED) (LED_2B high LED_2A low)SC1

LED1outU12none3.3VUSR (D13 green) SC1

LED2outV12none3.3VUSR (D14 green) SC1

LED3outW12none3.3VUSR (D15 green) SC1

LED4outV13none3.3VUSR (D16 red)SC1

MEM_SCLinW16none3.3VI2CSC1

MEM_SDAinoutV16none3.3VI2CSC1

MIO24
F5
1.8VMIO  / currently_not_usedSC2

MIO25
G5
1.8VMIO  / currently_not_usedSC2

MIO26outG15none3.3VMIO / PJTAG TCKSC1

MIO27outE12none3.3VMIO / PJTAG TDISC1

MIO28inE15up3.3VMIO / PJTAG TDOSC1

MIO29outC11none3.3VMIO / PJTAG TMSSC1

MIO30outC13down3.3VMIO / Status LEDSC1

MIO31inB12
3.3VMIO  / currently_not_usedSC1

MIO32
B11
3.3VMIO  / currently_not_usedSC1

MIO33inU7up3.3VMIO / PCIe ResetSC1

MIO34outD12none3.3VMIO / CAN
SC1

MIO35inF15up3.3VMIO  / CANSC1

MIO36
G7
3.3VMIO  / currently_not_usedSC1

MIO37
D14
3.3VMIO  / currently_not_usedSC1

MIO40
F12
3.3VMIO  / currently_not_usedSC1

MIO41
T8
3.3VMIO  / currently_not_usedSC1

MIO42outB14none3.3VMIO / UART RXSC1

MIO43inE7up3.3VMIO / UART TXSC1

MIO44outE14none3.3VMIO / SD-WPSC1

MIO45outA20none3.3VMIO / SD-CPSC1

MIO6inF6none1.8VMIO / QSPI FB CLK from ZynqMP, configured as  tristate high impendanz output SC2

MODE0outH3none1.8VPS Config Boot Mode SC2

MODE1outH2none1.8VPS Config Boot Mode SC2

MODE2outG2none1.8VPS Config Boot Mode SC2

MODE3outG1none1.8VPS Config  Boot Mode SC2

MRoutL7none1.8VPS Config (PS_POR_B)  ResetSC2

NCoutAA20none3.3Vused as dummi output pin / Not connectedSC1

FMCB_SENSEinT15none3.3VRPM inputSC1NC
FMCF_PWMoutV15none3.3VPWM outputSC1NC
FMCF_SENSEinW15none3.3VNot connectedSC1NC
FMCC_SENSEinV14none3.3VRPM inputSC1NC
FMCD_SENSEinW14none3.3VRPM inputSC1NC
FMCB_PWMoutU13none3.3VPWM outputSC1NC
FMCA_SENSEinT13none3.3VRPM inputSC1NC
FMCA_PWMoutAB16none3.3VPWM outputSC1NC
NC
Y3
3.3VNot connectedSC1

FMCE_SENSEinA21none3.3VRPM inputSC1NC
NC
G6
1.8VNot connectedSC2

NC
N1
1.8VNot connectedSC2

NC
N2
1.8VNot connectedSC2

NC
M1
1.8VNot connectedSC2

NC
N3
1.8VNot connectedSC2

NC
P2
1.8VNot connectedSC2

NC
M7
1.8VNot connectedSC2

NC
M6
1.8VNot connectedSC2

NC
P3
1.8VNot connectedSC2

NC
R1
1.8VNot connectedSC2

NC
M5
1.8VNot connectedSC2

NC
H5
1.8VNot connectedSC2

NC
J5
1.8VNot connectedSC2

NC
J4
1.8VNot connectedSC2

NC
K5
1.8VNot connectedSC2

NC
L3
1.8VNot connectedSC2

PG_12VinA11none3.3VPower 1 SC1

PG_FPDinA10none3.3VPower 2SC1

PG_GT_LinK3up1.8VPower 5BCSC2

PG_GT_RinF11up3.3VPower 5BCSC1

PG_PSGTinA5up3.3VPower 6A SC1

PHY_CLK125MinK2
1.8V / currently_not_usedSC2

NC
L5
1.8VNot connectedSC2PHY_LED0
NC
L1
1.8VNot connectedSC2PHY_LED1
NC
K1
1.8V / currently_not_usedSC2PHY_LED2
PLL_RSToutL4none1.8VReset SC2

PROG_BoutE2none1.8V PS Config (opt. PL Reset)SC2

PSGT_ENoutB10none3.3VPower 4ASC1

SC_SW1inE17none3.3VUSR S3-3 / Set Boot ModeSC1

SC_SW2inD16none3.3VUSR S3-4 / Set Boot Mode SC1

SD_CDinT11none3.3VSD CDSC1

SD_ENoutU11none3.3VPower 8SC1

SD_WPinT10none3.3VSD WPSC1

SFP_LED1
AB17
3.3V / currently_not_usedSC1

SFP_LED2
AB18
3.3V / currently_not_usedSC1

SFP_LED3
AA16
3.3V / currently_not_usedSC1

SFP_LED4
AB15
3.3V / currently_not_usedSC1

SFP0_LOS
V8
3.3V / currently_not_usedSC1

SFP0_TX_DISoutY7none3.3VSFPSC1

SFP1_LOS
W7
3.3V / currently_not_usedSC1

SFP1_TX_DISoutV7none3.3VSFPSC1

SI5345_CLK
E1
1.8V / currently_not_usedSC2

SSD1_LED
AA13
3.3V / currently_not_usedSC1

SSD1_PERSTNoutAA11none3.3VSSD Reset SC1

SSD1_SLEEP
AA12
3.3V / currently_not_usedSC1

SSD1_WAKEoutAB11none3.3VSSDSC1

U_SW1inD18
3.3VUSR (S4-1) / currently_not_usedSC1

U_SW2inD17
3.3VUSR (S4-2) / currently_not_usedSC1

U_SW3inC19
3.3VUSR (S4-3)/ currently_not_usedSC1

U_SW4inC18
3.3VUSR (S4-4) / currently_not_usedSC1

USB0_RSToutM2none1.8VReset SC2

USBH_MODE0outY17none3.3VUSBSC1

USBH_MODE1outY16none3.3VUSBSC1

USBH_RSToutY15none3.3VReset SC1

USR_BUT1inF13
3.3VUSR (S1)  / currently_not_usedSC1

USR_BUT2inG13none3.3VUSR (S2) / Power Reset SC1

USR_BUT3inW17up3.3VUSR (S3) / optional Power Reset SC1
N.C. on PCB REV02,REV03
XMOD1_AoutB19none3.3VXMOD J35 / currently_not_usedSC1

XMOD1_BoutA17none3.3VXMOD J35 LED / Attention this is connected to XMOD1_E SC1

XMOD1_EinC17
3.3VXMOD J35 / Attention this is connected to XMOD1_B  / currently_not_usedSC1

XMOD1_GinA18
3.3VXMOD  J35 Button  / currently_not_usedSC1

XMOD2_AoutK7none1.8VUART RXD (XMOD J24) SC2

XMOD2_BinK6none1.8VUART TX  (XMOD J24) SC2

XMOD2_EoutH7none1.8VXMOD J24 LED / Boot ModeSC2

XMOD2_GinH6none1.8VXMOD J24 Button / PS Reset SC2


Functional Description

JTAG FMC/CPLD

JTAG access over CPLD XMOD J35.

Set DIP-Switch S3-2 to ON to get CPLD into JTAG Chain. This is only needed for CPLD update. Otherwise JTAG is routed thought FMCs or to PJTAG dependign on boot mode. JTAG is connected into cascade from FMC A to F, if module is detected, otherwise corresponding connector is left out.

Boot ModeDescription
PJTAG0PJTAG MIOs are connected to JTAG chain
all otherFMC IOs are connected to JTAG chain

Note: FPGA/SoC JTAG access is available directly over second XMOD J24 with Label FPGA on TEB0911 connector.

Power

Power is controlled by different state machines and can be restart over S2 Button or S3 Button (PCB REV04 and newer only). Main Power sequence must be finished successfully before other power management units starts. Power Management can be checked over status LEDs, see LED section.

Main Power:

StateConditions for next stateDescription
1:IDLEPG_12V is ready

Start with this state on power up or Power Reset

  • EN12V is enabled, EN_VCCINT, EN_3P3V, DDR_EN are disabled
2:PER1_ENPG_FPD is ready
  • EN12V, EN_VCCINT, EN_3P3V are enabled, DDR_EN is is disabled
3:PER2_ENDDR_PG is ready
  • EN12V, EN_VCCINT, EN_3P3V DDR_EN are enabled 
4:RDYDDR_PG or PG_FPD or PG_12V failedNormal state if power sequence was ok.
5:ERROR---Only set, if a error occurs after successfully power up. Manually reset is needed.

MGT Power:

StateConditions for next stateDescription
1:IDLEMain Power sequence is done

Start with this state if main power is stared.

  • PSGT_EN, EN_GT_L, EN_GT_R are disabled
2:PER1_ENPG_PSGT, PG_GT_L, PG_GT_R are ready
  • SGT_EN, EN_GT_L, EN_GT_R are enabled
3:RDYPG_PSGT or  PG_GT_L or  PG_GT_R failedNormal state if power sequence was ok.
4:ERROR---Only set if a error occurs after successfully power up. Manually reset is needed.

Periphery Power:

StateConditions for next stateDescription
1:IDLEMain Power sequence is done

Start with this state if main power is stared.

  • DP_EN, EN_SFP_SSD, SD_EN are disabled
2:PER1_ENNo check possible, next state is RDY
  • DP_EN, EN_SFP_SSD, SD_EN are enabled
3:RDYNo check possibleNormal state if power sequence was ok.
4:ERROR---This state should never occurs.

FMC A and F Power:

StateConditions for next stateDescription
1:IDLEMain Power sequence is done

Start with this state if main power is stared.

  • FMC12V_EN, EN_AF_1V8, EN_A_3V3, EN_F_3V3, FMCF_PG_C2M, FMCA_PG_C2M are disabled
2:PER1_ENFMCAF_12V_PG and 5ms wait counter
  • FMC12V_EN, EN_AF_1V8, EN_A_3V3, EN_F_3V3, FMCF_PG_C2M, FMCA_PG_C2M are enabled
3:RDYFMCAF_12V_PG  failedNormal state if power sequence was ok.
4:ERROR---Only set if a error occurs after successfully power up. Manually reset is needed.

FMCF_PB_C2M, FMCC_PG_C2M, FMCD_PG_C2M, FMCE_PG_C2M are controlled via HW in PCB REV05

FMC B,C,D,E Power:

StateConditions for next stateDescription
1:IDLEMain Power sequence is done

Start with this state if main power is stared.

  • EN_BC_1V8, EN_DE_1V8, EN_B_3V3, EN_C_3V3, EN_D_3V3, EN_E_3V3, FMCB_PG_C2M, FMCC_PG_C2M, FMCD_PG_C2M, FMCE_PG_C2M are disabled
2:PER1_EN5ms wait counter
  • EN_BC_1V8, EN_DE_1V8, EN_B_3V3, EN_C_3V3, EN_D_3V3, EN_E_3V3, FMCB_PG_C2M, FMCC_PG_C2M, FMCD_PG_C2M, FMCE_PG_C2M are enabled

3:RDY---Normal state if power sequence was ok.

FMCF_PB_C2M, FMCC_PG_C2M, FMCD_PG_C2M, FMCE_PG_C2M are controlled via HW in PCB REV05


Reset

ButtonDescription
S2Main Power Reset Button. Restart power management.
FPGA XMODPS MR  Reset Button. Restart PS (PS_POR_B)
  • Buttons are debounced.

For all other resets, see component sections.

Boot Mode

S3-3 (SC_SW1)S3-4 (SC_SW2)Description
OFFOFFSD1 Boot Mode (SD-Card on J11), if SD is insert
OFFOFFeMMC Boot Mode, if SD is not insert
OFFONPJTAG0
ONOFFQSPI32
ONONJTAG


Display Port

OutputInput
DP_AUX_TXB66_T1
DP_AUX_DEnot B66_T2
B66_T3DP_AUX_RX
B67_T1DP_TX_HPD

CAN

  • CAN_S soured by B65_T1
  • CAN_FAULT is connected to B65_T2
  • CAN_RX is connected to MIO34
  • CAN_TX  sourced by MIO35

SD

  • SD_EN is controlled by power management.
  • SD_CD is connected to MIO45.
  • SD_WP is connected to MIO44.

SFP

  • Transmit for all SFP is enabled.

USB

  • USB Mode pins constant "11" (default boot mode).
  • USB0_RST is controlled by power management.
  • USBH_RST is controlled by power management.

SSD

  • SSD1_WAKE is "0".
  • SSD1_PERSTn is controlled by power management and MIO33.

I2C

CPLD contains treww soft IP I2C interfaces. One info core and two emc02305 fan controller emulator. I2C_RST is controlled by power management.

 I2C Info Core

I2C info core provide basic CPLD information and is read only.

I2C address: 0x20

Register addressContent
0x00Major CPLD Revision
0x01Minor CPLD Revision
0x02Boot Mode <br> 0x00 JTAG <br>0x02  QSPI <br> 0x08 PJTAG_0 <br> 0x06 eMMC <br> 0x05 SD1
0x03-0x06GIT Hash bit 31-0


FAN - EMMC230x
Emulated Controller support following features
  • PWM configuration:
    • polarity (0x2a) and output register (0x2b) configuration
    • base CLK selection (0x2c, 0x2d)
    • divider (0x[x]1; [x=3..7])
    • PWM setting (0x[x]0; [x=3..7])
  • FAN tach configuration:
    • range and edge control (0x[x]2; [x=3..7])
    • tach value (0x[x]e;0x[x]f; [x=3..7])
  • Status register
    • product feature (0xfc)
    • i2c address: only for emc supported address (hdl IP support more addresses)
    • default fan: nearest match only (hdl IP support any default pwm setup)
    • product id (0xfd), manufacturer id(0xfe) and revision (0xff)

For more register details see: EMC2301-2-3-5-Data-Sheet-DS20006532A.pdf  

FAN Controller 1

I2C address: 0x2E

FANAddress Offset
FAN F1 (J2)0x30
FAN F2 (J23)0x40
FAN F3 (J33)0x50
FAN FMCA (J10/J14)0x60
FAN FMCB (J4/J37)0x70
FAN Controller 2

I2C address: 0x2F

FANAddress Offset
FAN FMCC (J8/J38) 0x30
FAN FMCD (J7/J39)0x40
FAN FMCE (J6/J40)0x50
FAN FMCF (J21/J41)0x60
NC--

FAN

CPLD includes two EMMC305 emulators to control all 9 FAN (with PCB Revision 5).  See I2C section.

Note: For older PCB Revision 04 only FAN F1...F3 are controlable.

FMC

FMC present (FMCx_PRESNT) signals are used for board detect and enables FMC JTAG and FMC FAN Power.  A chain between every connected FMC Card is created. 

FMC JTAG: See JTAG FMC/CPLD section

FAN : See FAN and I2C section


UART

UART is connected to FPGA XMOOD on J24. XMOD UART RXD output is connected to MIO42. MIO43 is connected to XMOD UART TX input.

USR Buttons and Switches


LED

LEDDescription
LED4 (D16 red)

User FPGA IO B67_T3

LED3 (D15 green)User FPGA IO B67_T2
LED2 (D14 green)

PS Status. Status depends on blink sequence and priority.

  1. ********    : Reset button is pressed
  2. *****ooo   : Init_B failed
  3. ****oooo   : PS_Error_Status and PS_Error failed
  4. ***ooooo   : PS_Error_Status failed
  5. **oooooo  : PS_Error failed
  6. *ooooooo  : Done is low-> SoC PL not programmed
  7. LED OFF or ON :  user defined from MIO30
LED4 (D13 green)Power LED. Status depends on blink sequence and priority.
  1. LED OFF: Power button is pressed (Note, 1 and 8 are swapped with CPLD REV03)
  2. ********    : Main power up failed
  3. *****ooo   : Main power error after successfully startup
  4. *****ooo   : MGT or Periphery power up failed
  5. ***ooooo  : MGT or Periphery power error after successfully startup
  6. **oooooo  : FMC power up failed
  7. *ooooooo : FMC 12V power for FMCA AF
  8. LED ON: Power good (Note, 1 and 8 are swapped with CPLD REV03)
FPGA XMOD (J24-XMOD2 D4 red)

Boot Mode. Status depends on blink sequence and priority.

  1. LED ON  : JTAG
  2. ********    : Error unknown state
  3. ***ooooo  : eMMC
  4. **oooooo  : QSPI
  5. *ooooooo : PJTAG_0
  6. LED OFF : SD1
CPLD XMOD (J35-XMOD1 D4 red)
  1. ********    :  FMC card connected and PG from FMC card failed
  2. *****ooo  : FMC card connected and FMC FAN disabled and FAN1..3 is disabled
  3. ****oooo  : FMC card connected and FMC FAN disabled and FAN1..3 is OK
  4. ***ooooo : FMC card connected and FMC FAN OK and FAN1..3 is disabled
  5. LED OFF : all connected FMCx_PG_M2C are ready and FAN are enabled

Note: * means LED pulse and = means break. Example: ***00000 means LED three times flash on followed by a break from five time a break where LED is off

Appx. A: Change History and Legal Notices

Revision Changes

CPLD REV05 to REV6.0

  • extend Firmware revision to Major and Minor number
  • update I2C Slave IP
    •  bugfixes read support and address incrimination
  • replace FAN controller logic with emc230x emulator ip
    • extend to FMCA-F FAN
  • add IP for LED blink sequence
  • add debounce IP for buttons and PG signals 
    • reduce debounce time for buttons to 21ms
    • set debounce time for PG signals to 500us
  •   add FMC JTAG max delay constrains
  •   add I2C Info core read out firmware information via I2C
  •   cleanup code
    • remove unused logic
    • set unused IOs as comment for later usage
  • set MIO6 as high impedance output
  • remove PHY LED signals and logic (not longer connected on PCB REV05)
  • change FMC power up sequencing (changes on PCB REV05)
    • remove FMCx_PG_C2M monitoring
    •    add delay counter to release monitoring IC for FMCx_PG_C2M
  •   change MEM_SCL from pulldown to pullnone (external pullup)
  •   bugfix swap FAN_A_EN and FAN_F_EN
  •   LED
    •  add FAN disabled status to J35 (LED XMOD1 SC) 
    • add emmc boot mode to J24 LED (XMOD2 FPGA)

CPLD REV04 to REV05

  • add can

  • DP_TX_HPD input pin threshold changed

CPLD REV03 to REV04

  • bugfix FMC JTAG (support multiple device in the chain now)

CPLD REV02 to REV03

  • add main Reset to optional User Button 3 (only on PCB REV04 usable)
  • add PHY LEDs
  • add emmC Boot Mode
  • new I2C controller
  • swapped LED1 0,7 state (LED ON is ready now)

CPLD REV01 to REV02

  • Correction of FAN_A_EN and FAN_AF_EN Location constrains

  • Add Pullup attribute to FMCX_PRSNT signals

  • I2C Enable mapping is changed

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.


DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescriptionFirmware Release

REV6.0REV05, REV04 (with limitations)
  • firmware update
  • SC-PGM-TEB0911-5_4_SC0911-6P0_default_20260127

2019-09-10

v.30

REV05REV02, REV03, REV04

John Hartfiel

  • firmware update
  • released at 2019-09-10

2018-12-10v.29REV04REV02, REV03, REV04John Hartfiel
  • firmware update
  • released at 2018-12-06

2018-11-19

v.28REV03REV02, REV03, REV04John Hartfiel
  • firmware update
  • released at 2018-11-19

2018-02-02

v.24REV02REV02, REV03John Hartfiel
  • add PCB REV03 support

2017-09-18v.23REV02REV02John Hartfiel
  • Revision 02 finished

2017-08-16v.21REV01REV02John Hartfiel
  • Revision 01 finished

2017-07-25v.1REV01REV02
  • Initial release


All



Legal Notices

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Product Disclaimer

Products (incl. Software and Firmware) are exclusively designed, manufactured, and distributed for industrial applications. They are not intended, authorized, or certified for use in critical safety applications, medical devices, aerospace, nuclear, life-support, traffic-control, military, or other environments where malfunction or failure could result in personal injury, death, or significant property or environmental damage.

Trenz Electronic GmbH (“Manufacturer”) excludes any liability for inappropriate use in such contexts. The Customer bears all responsibility for verifying suitability and compliance with applicable regulations when deploying in any critical-use scenario. The Customer also agrees to indemnify and hold harmless the Manufacturer from any third-party claims or liabilities arising from such use.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.




Table of contents