Table of Contents
Trenz Electronic GigaBee XC6SLX series are industrial-grade FPGA micromodules integrating a leading-edge Xilinx Spartan-6 LX FPGA, Gigabit Ethernet transceiver (physical layer), two independent banks of 16-bit-wide 128/512 MBytes DDR3 SDRAM, 16 MBytes SPI Flash memory for configuration and operation, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os is provided via robust board-to-board (B2B) connectors.
All this on a tiny footprint, smaller than half a credit card, at the most competitive price.
Block diagram of the GigaBee XC6SLX board
- Xilinx Spartan-6 LX FPGA
- clock generator
- 10/100/1000 Mbps Ethernet PHY
- protected 1-Wire EEPROM
- DC-DC converters
- B2B connector J1
- B2B connector J2
- Flash memory
Industrial-grade Xilinx Spartan-6 LX FPGA micromodule (LX45 / LX100 / LX150)
10/100/1000 tri-speed Gigabit Ethernet transceiver (PHY)
2 x 16-bit-wide 1 Gb (128 MB) or 4 Gb (512 MB) DDR3 SDRAM
128 Mb (16 MB) SPI Flash memory (for configuration and operation) accessible through:
1 kb protected 1-Wire EEPROM with SHA-1 Engine
JTAG port (SPI indirect)
FPGA configuration through:
SPI Flash memory
Plug-on module with 2 × 100-pin high-speed hermaphroditic strips
Up to 52 differential, up to 109 single-ended (+ 1 dual-purpose) FPGA I/O pins available on B2B strips
4.0 A x 1.2 V power rail
1.5 A x 1.5 V power rail
125 MHz reference clock signal
Single-ended custom oscillator (option)
eFUSE bit-stream encryption (LX100 or larger)
1 user LED
Evenly-spread supply pins for good signal integrity
Additional assembly options are available for cost or performance optimization upon request.
Initial Delivery State
Storage device name
SPI Flash memory
protected 1-Wire EEPROM
Power consumption of GigaBee XC6SLX modules highly depend on the FPGA design implemented. Some typical power consumptions are provided below for the following reference systems:
Boards – GigaBee XC6SLX 45/100/150
Base board – TE0603-02
Power supply – 5 V from baseboard
Connected Gigabit Ethernet cable
|FPGA type||Unconfigured||Configured with Web-server reference design|
|LX45||0.15 A||0.6 A|
|LX100||0.17 A||0.5 A|
|LX150||0.2 A||0.5 A|
The nominal supply voltage of the GigaBee XC6SLX is 3.3 volt. The minimum supply voltage is 3.0 volt. The maximum supply voltage is 3.45 volt.
Supply voltages beyond the range might affect to device reliability, or even cause permanent damage of the device!
Board power supply diagram
Power Supply Sources
GigaBee XC6SLX board must be powered at least in one of the following two ways:
- through B2B connector J1 (pins 1, 3, 5, 7, 9, 11, 13, 15),
- through B2B connector J2 (pins 2, 4, 6, 8, 10, 12).
We recommend to supply the module with all these 14 pins. When one or more of these pins are not power supplied, it or they can be used as power source for user applications.
Please make sure that your logic design does not draw more RMS current per pin than specified in section Board-to-board Connectors.
FPGA banks VCCIO power supply
FPGA VCCIO power options are shown below. Default values for configurable voltages are shown in braces.
VCCIO 0 (3.3 V)
|B1||VCCIO 1 (1.5 V)|
Bank 0 power supply VCCIO 0 can be configured by user to 3.3 V, 2.5 V or 1.5 V, see Chapter VCCIO0 Power Rail. Bank 1 VCCIO supply voltage is configured to 1.5 V to communicate with DDR3 SDRAM memory chip.
By special request, modules can be supplied without DDR3 SDRAM chips. Contact Trenz Electronic support for details.
On-board Power Rails
GigaBee XC6SLX has the following power rails on-board.
|3.3V Power Rail|
It is the main internal power rail and must be supplied from an external power source.
It supplies the other following power rails:
|1.2V Power Rail|
It is converted from the 3.3V rail by a switching voltage regulator and can provide up to 4.0 A to:
|1.5V Power Rail|
It is converted from the 3.3V rail by a switching voltage regulator and can provide up to 1.5 A to:
|2.5V Power Rail|
It is converted from the 3.3V rail by a linear voltage regulator and can provide up to 0.8 A to:
|VCCAUX Power Rail|
It is converted from the 3.3V rail by a linear voltage regulator and can provide up to 0.8 A to:
|VCCIO0 Power Rail|
There are 4 options to supply this rail:
Figure below show simplified schematic of power options. Dashed resistors are not populated by default.
Table below summarizes power rails information.
J1 (≤1.2 A)
|2.5V||2.5||0.8||3.3V ? linear||Ethernet|
J1 (≤0.3 A)
|1.5V||1.5||1.5||3.3V ? switch|
|J1 (≤0.3 A)|
|1.2V||1.2||4.0||3.3V ? switch|
|J1 (≤0.6 A)|
|VCCAUX||2.5||0.8||3.3V ? linear||FPGA||J2 (≤0.3 A)|
|VCCCIO0||1.2, 1.5, 1.8, 2.5, 3.3||0.9||J2||VCCO (0)||J2 (≤0.9 A)|
During power-on, the /RESET line is first asserted. Thereafter, the supply voltage supervisor monitors the power supply rail 3.3V and keeps the /RESET line active (low) as long as the supply rail remains below the threshold voltage (2.93 volt). An internal timer delays the return of the /RESET line to the inactive state (high) to ensure proper system reset prior to a regular system start-up. The typical delay time td of 200 ms starts after the supply rail has risen above the threshold voltage.
After this delay, the /RESET line is reset (high) and the FPGA configuration can start. When the supply rail voltage drops below the threshold voltage, the /RESET line becomes active (low) again and stays active (low) as long as the rail voltage remains below the threshold voltage (2.93 volt). Once the rail voltage raises again and remains over the threshold voltage for more than the typical delay time td of 200 ms, the /RESET line returns to the inactive state (high) to allow a new system start-up.
GigaBee XC6SLX integrates a power-fail comparator which can be used for low-battery detection, power-fail warning, or for monitoring a power supply other than the main supply 3.3 V. When the voltage of the PFI (power-fail comparator input, input pin 16 of connector J2) line drops below 1.25 volt, the /PFO (power-fail comparator output, FPGA pin A2, label IO_L83P_3) line becomes active (low). The user application can sense this line to take action. To set a power fail threshold higher than 1.25 volt, the user can implement a simple resistive voltage divider on the carrier board.
These connectors are hermaphroditic. Odd pin numbers on the module are connected to even pin numbers on the baseboard and vice versa.
4 x 5 modules use two or three Samtec Razor Beam LSHM connectors on the bottom side.
- 2 x REF-189016-02 (compatible to LSHM-150-04.0-L-DV-A-S-K-TR), (100 pins, "50" per row)
- 1 x REF-189017-02 (compatible to LSHM-130-04.0-L-DV-A-S-K-TR), (60 pins, "30" per row) (depending on module)
Connector Mating height
When using the same type on baseboard, the mating height is 8mm. Other mating heights are possible by using connectors with a different height
|Order number||Connector on baseboard||compatible to||Mating height|
The module can be manufactured using other connectors upon request.
Connector Speed Ratings
The LSHM connector speed rating depends on the stacking height; please see the following table:
|Stacking height||Speed rating|
|12 mm, Single-Ended||7.5 GHz / 15 Gbps|
|12 mm, Differential|
6.5 GHz / 13 Gbps
|5 mm, Single-Ended||11.5 GHz / 23 Gbps|
|5 mm, Differential||7.0 GHz / 14 Gbps|
Current rating of Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).
Connector Mechanical Ratings
- Shock: 100G, 6 ms Sine
- Vibration: 7.5G random, 2 hours per axis, 3 axes total
GigaBee XC6SLX board contains a Maxim DS2502-E48 node address chip with factory-programmed valid MAC-48 address and 768 bits of OTP-EPROM memory for user data.
Address chip provide convenient data access through 1-Wire interface up to 16.3 kbps (FPGA pin T11).
More information can be found in the Maxim DS2502-E48 product overwiew.
Additional 1Kb protected 1-Wire EEPROM with SHA-1 engine DS2432 accessible via the same line.
More information can be found at the Maxim DS2432 product page.
DDR3 SDRAM Memory
The board contains two 1 Gb (128 MB) or 4 Gb (512 MB) DDR3 SDRAM chips. Data width of each chip is 16 bit. DDR3 memory connected to FPGA bank 1 and FPGA bank 3. Spartan-6 Memory controller Blocks operations can be merged to implement effective 32-bit memory interface. Refer Xilinx XAPP496 for detailed information.
GigaBee XC6SLX board contains 128 Mb (16 MB) serial flash memory chip Winbond W25Q128FV (W25Q128BV till REV 02) (U11). This serial flash chip can operate as general SPI memory mode and in double or quad modes. Usage of dual and quad modes increase bandwidth up to 40 MB/s.
For more information see Winbond W25Q128FV (W25Q128BV till REV 02) product overview.
Flash can be programmed in several ways:
- Direct SPI programming via J1 connector.
- Indirect SPI programming via FPGA pins, controlled by JTAG.
- Direct SPI programming by FPGA, using SPI core.
Serial flash is connected to FPGA bank 2 and B2B connector J1; used pins are listed in the table below.
|Flash signal||FPGA pin||J1 pin|
Serial flash signals connection
The board contains a Marvell Alaska Ethernet PHY chip (88E1111) operating at 10/100/1000 Mb/s. The board supports GMII interface mode with the FPGA. Configuration details:
- PHY address – 00111
- Do not advertise the PAUSE bit
- Auto Neg
- Advertise all caps
- Prefer slave
- Auto crossover
- 125clk - enabled
- GMII to copper
- Fiber auto-detect - disabled
- Sleep mode - disabled
Ethernet signals from PHY are connected to B2B connector J1. To use Ethernet in your design, GigaBee module should be connected to the carrier board, which have Ethernet magnetics and RJ45 connector. TE0603 carrier board can be used to access Ethernet capabilities of GigaBee XC6SLX series modules.
For correct operation of the Marvell PHY it is required that PHY Reset pin sees valid low level each time power is applied and also during any brownout situations where system Power is removed for short time, but some pins are not at valid logic levels.
- if GbE PHY is not used PHY reset pin can be tied off to GND
- if PLL is used from PHY clock, then PLL "locked" output can be used to reset PHY - as long PLL is not locked, it will keep PHY in reset
- Reset pulse generation circuit clocked from FPGA internal configuration clock, this circuit can force PHY reset pin to low when external clock from PHY is not available
- any custom Reset circuit that is guaranteed to drive PHY reset to low level at least once after FPGA configuration when PHY clock is not running.
- any user logic that is guaranteed to drive PHY reset low after FPGA configuration (without using PHY clock).
Explanation: Marvell PHY samples the MODE pins ONLY when it sees low level on PHY reset input, it does not sample those pins during short power off situations (if the reset pin holds high level because of pin capacitance and high impedance of the pins)! So it is possible that the PHY mode is reset, but the mode pins are not sampled again - this yields in mode setting where 125MHz reference clock from PHY is not available.
The module has one 25 MHz oscillator for Ethernet PHY (U9). Ethernet PHY provides clock multiplication and resulting 125 MHz clock acts as a system and user clock for the FPGA (FPGA input pin AA12).
Note: For correct generation start, PHY should receive reset pulse. Recommended way to do it it's to connect PHY reset signal (ETHERNET_PHY_RST_N) to LOCKED output of corresponding DCM (DCM which use 125 MHz from PHY).
The module also provides the footprint for custom 3.3 V single-ended oscillator (U12) which can be installed as an option (FPGA input pin Y13).
The module contains one user active-low LED connected to FPGA output pin T20. To access more LEDs, use a carrier board and drive FPGA signals connected to B2B connectors. As LED connected to FPGA bank with configurable VCCIO to light LED FPGA pin should in '0' (low) state. To disable LED FPGA pin should be in 'Z' (High impedance).
GigaBee XS6LX has a watchdog timer that is periodically triggered by a positive or negative transition of the WDI (watchdog input) line (FPGA pin V9). When the supervising system fails to re-trigger the watchdog circuit within the time-out interval (min 1.1 s, typ 1.6 s, max 2.3 s), the /WDO (watchdog output) line becomes active (low). This event also re-initializes the watchdog timer.
If zero-resistors R2 is not assembled, the watchdog is disabled (alternate assembly).
If zero-resistors R2 is assembled, the watchdog can be enabled (standard assembly). In this case there is still two options:
To enable the watchdog, after module power-up, drive the WDI signal to generate at least one transition (no matter positive or negative).
To keep watchdog disabled, set WDI FPGA signal output to high-impedance. One way to reach this goal is to leave FPGA pin V9 (label IO_L50N_2) undeclared in user constrains file (UCF) and set “unused IOB pins” to “float” in the Xilinx Project Navigator options, see Fig. below.
(Project properties > Configuration options > Unused IOB Pins > Float).
Unused IOB Pins option selection.
In the standard assembly, the /WDO (watchdog output) line is left unconnected1 and the only possibility to reset the module is by driving the /MR (master reset) line active (low) through pin 18 of connector J2.
In the alternate assembly, the /WDO (watchdog output) line is connected through zero-resistor R3 to /MR (master reset) line.
If alternate assembly is used, pin 18 of connector J2 must be left unconnected.
The FPGA on GigaBee XC6SLX board can be configured by means of the following devices:
- Xilinx download cable (JTAG)
- SPI Flash memory
The FPGA can be configured through the JTAG interface. JTAG signals are connected to B2B connector J2. When GigaBee XC6SLX board is used with the TE0603 carrier board, the JTAG interface can be accessed via connectors J5 and J6 on the carrier board.
Default configuration option for FPGA is “Master Serial/SPI”. The bit-stream for the FPGA is stored in a serial Flash chip (U11). See chapter 2.7 Flash Memory for additional information.
eFUSE programming feature is not directly supported by GigaBee XC6SLX modules, but it is possible to use it. To program eFUSE, please follow the steps below:
- Connect VCCAUX to 3.3V power rail.
On TE0603 it can be done by connecting J5 pin 2 or J6 “VREF” (VCCAUX) to J1 any pin from 1,2,3,4 (3.3V). See Figure below.
- Program eFUSE using JTAG cable and iMPACT software.
- Remove power supply connections to VCCAUX
B2B Connectors Pin Descriptions
This section describes how the various pins on B2B connectors J1 and J2 connects to TE0600 on-board components. There are five main signal types connected to B2B connectors:
- FPGA users signals;
- FPGA system signals;
- Power signals;
- Ethernet PHY signals;
- Other system signals.
|Bank 0||1||22||45||VCCIO 0 (3.3 V)|
|Bank 1||1||6||13||VCCIO 1 (1.5 V)|
|Bank 2||3||21||45||3.3 V|
|Bank 3||0||3||6||1.5 V|
B2B signals count
FPGA user signals connected to B2B connectors are characterized by the "B2B_Bx_Lyy_p" naming convention, where:
- B2B defines a "FPGA to B2B" signal type;
- Bx defines the FPGA bank (x = bank number);
- Lyy defines a differential pair or signal number (yy = pair number);
- p defines a differential signal polarity (P = positive, N = negative); single ended signals do not have this field.
Ethernet PHY signals use "PHY_name" naming conversions where "PHY" defines signal type "PHY to B2B" and "name" is PHY signal name.
Remaining signals use custom names.
Note that GigaBee XC6SLX have hermaphroditic B2B connectors. A feature of hermaphroditic connector numbering is that connected signal numbers don't match. Odd signals on module connect to even signals on baseboard. For example module signal 1 to baseboard signal 2, module signal 2 to baseboard signal 1, module signal 3 to baseboard signal 4 and so on.
Most pins of B2B connectors J1 and J2 are general-purpose, user-defined I/O pins (GPIOs). There are, however, up to 8 different functional types of pins on the TE0600, as outlined in Table below. In pin-out tables Table 11 and Table 12, the individual pins are colour-coded according to pin type as in Table below.
TE0600 pin types
|DIO||Unrestricted, general-purpose differential user-I/O pin.|
|SIO||Unrestricted, general-purpose user-I/O pin.|
|CONFIG||Dedicated configuration signals.|
|PWRMGMT||Control and status signals for the power-saving Suspend mode.|
|JTAG||Dedicated JTAG signals.|
|GND||Dedicated ground pin. All must be connected.|
|TE||Trenz Electronic specific pin type.|
See the description of each pin in the user manual for additional information on the corresponding signals.
|PHY||Ethernet PHY signals.|
Note that some of Spartan-6 I/O types are partially compatible, so pins of compatible types can be used as inputs for signal of other type. For example pins from FPGA bank with 1.5V VCCO (IOSTANDARD = LVCMOS15) can be used as inputs for 1.2V, 1.8V, 2.5V and 3.3V signals.
See “Spartan-6 FPGA SelectIO Resources” page 38 for detailed information.
External Bank 2 differential clock connection
TE0600-02 module have optional connection to FPGA bank 2 differential clock input pins. To provide connection from B2B_B2_L41_P signal to Y13 FPGA pin, zero-resistor R69 should be soldered. To provide connection B2B_B2_L41_N signal to AB13 FPGA pin, zero-resistor R81 should be soldered. Note that in this case optional user oscillator U13 can't be used.
|Net Length||J1 pin||Net||Type||FPGA pin||Net Length|
|J2 pin||Net||Type||FPGA pin||Net Length||J2 pin||Net||Type||FPGA pin||Net Length|
Signal Integrity Considerations
Traces of differential signals pairs are routed symmetrically (as symmetric pairs).
Traces of differential signals pairs are NOT routed with equal length, although difference in signal lines length is negligible for actual signal frequencies. For applications where traces length has to be matched or timing differences have to be compensated, Tables below list the trace length of I/O signal lines measured from FPGA balls to B2B connector pins.
Traces of differential signals pairs are routed with a differential impedance between the two traces of 100 ohm. Single ended traces are routed with 60 ohm impedance.
An electronic version of these pin-out tables are available for download from the Trenz Electronic support area of the web site.
Module revisions and assembly variants
Module revision coded by 4 FPGA BR[3:0] pins, which can be read by FPGA firmware. All these pins should be configured to have internal PULLUP.
Board revisions pin coding
Main differences between 01 and 02 revisions:
- More powerful regulators for 1.2V and 1.5V rails
- VCCAUX separated from 2.5V power rail
- 128Mbit SPI Flash
- Additional secure 1Kbit EEPROM
- Optional B2B connection to bank 2 differential clock input
Main differences between 02 and 03 revisions:
- Optimized placement and routing for DC/DC converters
- Added thermal vias to mounting holes
- Added Testpoints
- Changed Board revision identification to REV03
- Changed U9 from SIT1602AI-83-33E-25.0000 to SiT8008AI-73-XXS-25.000000E
- Added Track-it™ Traceability Pad
- Change SPI Flash from W25Q128BVEIG to W25Q128FVEIG
- DDR3 changed from IM4G16D3EABG-125I to IM4G16D3FABG-125I for the 4 GBit variants
- U13 (DS2432P+) is no longer populated by default
Module assembly variants coded by 4 zero ohm resistors, connected to FPGA AV[3:0] pins. All these pins should be configured to have internal PULLUP.
Assembly variants pin coding
Related Materials and References
The following documents provide supplementary information useful with this user manual.
Xilinx DS160: Spartan-6 Family Overview
This overview outlines the features and product selection of the Spartan®-6 family.
Xilinx DS162: Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
This data sheet contains the DC and switching characteristic specifications for the Spartan®-6 family.
Samtec Razor Beam LSHM series overview.
Maxim DS2502-E48 product overview.
Winbond W25Q128BV product overview.
Maxim DS2432 product page.
Xilinx Spartan-6 Documentation
Trenz Electronic GigaBee Series Documentation
Xilinx UG380: Spartan-6 FPGA Configuration User Guide
This all-encompassing configuration guide includes chapters on configuration interfaces (serial and parallel), multi-bitstream management, bitstream encryption, boundary-scan and JTAG configuration, and reconfiguration techniques.
Xilinx UG381: Spartan-6 FPGA SelectIO Resources
Design and Development Tools
Trenz Electronic GigaBee Design Resources
Trenz Electronic GigaBee Reference Designs
Xilinx UG695: ISE In-Depth Tutorial
Chapter 8: Configuration Using iMPACT
Glossary of Abbreviations and Acronyms
|A WARNING notice denotes a hazard. It calls attention to an operating procedure, practice, or the like that, if not correctly performed or adhered to, could result in damage to the product or loss of important data. Do not proceed beyond a WARNING notice until the indicated conditions are fully understood and met.|
|A CAUTION notice denotes a risk. It calls attention to an operating procedure, practice, or the like that, if not correctly performed or adhered to, could result in a fault. (undesired condition that can lead to an error) Do not proceed beyond a CAUTION notice until the indicated conditions are fully understood and met.|
application programming interface
digital signal processing; digital signal processor
Embedded Development Kit
input / output blocks; I/O blocks
Software Development Kit
Xilinx Platform Studio
GigaBee XC6SLX can reach a minimum vertical height of about 8 mm, if B2B connectors are not assembled. The maximum component height on the module board on the top side is about 3.5 mm. The maximum component height on the module board on the bottom side is about 3.0 mm.
The typical minimum and maximum height from the carrier board surface, of a GigaBee XC6SLX when it mounted on a carrier board, is respectively about 5.0 mm and about 13 mm.
GigaBee XC6SLX has 4 mounting holes, one in each corner. The module can be fixed by screwing M3 screws (ISO 262) onto a carrier board through those mounting holes.
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Industrial grade: -40°C to +85°C.
The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
GigaBee XC6SLX weighs between 17.1 and 17.3 g with standard connectors.
Document Change History
|2011-10-05||0.02||AIK||Added B2B pin-out section.|
|2011-10-06||0.03||AIK||Reformatted pin-out tables. Added eFUSE programming section.|
|2011-10-06||0.04||AIK||Added board photos. Additions to eFUSE section.|
|2011-10-06||0.05||AIK||Removed net length information for nets which can't be measured right.|
|2011-10-06||0.06||AIK||Added power consumption section.|
|2011-10-08||0.07||AIK||Little fixes after FDR audit.|
|2011-10-12||0.08||AIK||Fix in eFUSE section.|
|2011-11-11||0.09||AIK||Added pin numbering description for B2B connectors|
|2012-01-20||0.10||AIK||Added pin compatibility note and manual reference.|
|2012-04-12||0.11||AIK||Added FPGA banks VCCIO voltages table.|
|2012-04-17||1.00||FDR||Updated documentation link.|
Replaced obsolete ElDesI and RedMine links with current GitHub links.
Updated dating convention.
|2012-05-18||1.01||AIK||Corrected cross-reference in section 3.2. Corrected LED description.|
|2012-06-18||1.02||FDR||Removed junction temperature limits under connector current ratings.|
|2012-07-18||1.03||AIK||Added table with B2B signals summary per FPGA bank|
|2012-10-30||2.01||AIK||Fork to 01 and 02 board revisions|
|2012-11-06||2.01||AIK||Fixed bank 1 power options|
|2012-11-21||2.02||AIK||Updated module diagram|
|2012-11-30||2.03||AIK||Added Ethernet disable note|
|2012-12-19||2.04||AIK||Fixed SPI Flash size on block diagram|
|2013-01-21||2.05||AIK||Added PHY reset note|
|2013-03-13||2.06||AIK||Connectors current chapter moved to separate document|
|2013-03-13||2.07||AIK||Changed Bank 1 power supply description and VCCIO0 sources description|
|Pause advertise correction|
|Document ported to wiki and adapted to web presentation.|
|2017-04-03||TT||Added REV03 to assembly Variant Table|
Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy
The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.
Limitation of Liability
In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.
No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.
The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.
To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.
REACH, RoHS and WEEE
Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).
Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.
Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).
Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.