This document provides a brief overview of the required board configuration (DIP switches, jumpers, etc.) for each supported module when used with the TE0703 carrier board. It describes the settings required for each module, including the boot mode configuration where applicable.

DIP/Jumper/ButtonTE0703-07...TE0821-02
S1RESIN is driven by S1 (Push Button) and push button will force to GND. Button is debounced. 

S2
DIP*Description
S2-1(A)CM1 (Used to change PGOOD pin state /If CM1 set to high (S2-1 OFF) → PGOOD = '1' otherwise '0') 
S2-2(B)CM0 (used as JTAG Selection/ If CM0 set to high (S2-2 OFF) → Access to CPLD of module otherwise access to FPGA of module.)
S2-3(C)JTAGEN (Enable JTAG access to CPLD for Firmware update (zero: normal IOs, one: CPLD JTAG access))
S4-4(D)MIO0 (Used as Boot Mode)



Boot Mode*QSPISDeMMCJTAG
S2-1OFFOFFONON
S2-4OFFONOFFON
Phy LEDglow greenglow orangeflashflash

TE0703 CPLD - CC703S#CC703S-BootMode

JTAG MUXCarrier CPLD Module CPLDModule SoC
S2-2ON/OFFOFFON
S2-3OFFONON

TE0703 CPLD - CC703S#CC703S-JTAG

  * Module CPLD Firmware depended

J5, J8, J9, J10

VCCIO A..D Power supply

JumperB2B Bank Pin
J5 (VCCIOA)JB1-10/12
J8 (VCCIOB)JB2-2/4
J9 (VCCIOC)JB2-6
J10 (VCCIOD)JB2-8/10

(1-2=3.3V/2-3=1.8V)


  • M1.8V
Jumper1.8V3.3V
J5 (JM1-9/11 VCCO_HD25_26)1-22-3
J8 (JM2-1/3 not connected)not connectednot connected
J9 (JM2-5 VCCO_65)1-2do not use, out off range!
J12 (JM2-7/9 VCCO_HD24_44)1-22-3
J11
  • SD Level Shifter (2-3=3.3V/1-2=1.8V)

  • M3.3V
J7
JumperB2B Bank Pin
J7 (VBAT)JB1-80

(1-2/2-3=GND)


  • open
CPLD Dependencies

yes


yes

HW Revision DependenciesTE0703 Product Change Notifications

TE0821 Product Change Notifications

yes

  • different connection to CPLD, see CPLD dependencies

* Close Dip (ON) will force to GND