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CompanyTrenz Electronic GmbH
PCN NumberAVN-20220802
TitleAVN-20220802 QSPI boot problem at slow rise time of module input voltage
Subject
Issue Date

AVN-20220802

Products Affected

This issue can happens on following Trenz Electronic SoMs with native FPGA:

Affected Product

NoteNote
TE07104x5 Seriesissue fixed Revision 3 and newer with Diode between PROG_B and INT_B
TE07114x5 Seriesissue fixed Revision 2 and newer with Diode between PROG_B and INT_B
TE07124x5 Seriesissue fixed Revision 4 and newer with Diode between PROG_B and INT_B
TE07134x5 Seriesissue fixed Revision 3 and newer with Diode between PROG_B and INT_B
TE07143x5 Series
VCCIO_0 is no sourced by internal 1.8V
issue fixed Revision 4 and newer with Diode between PROG_B and INT_B
TE07414x5 Seriesissue fixed Revision 5 and newer with Diode between PROG_B and INT_B
TE08414x5 Seriesissue fixed Revision 3 and newer with Diode between PROG_B and INT_B


Description: 

On 4x5 Module power switch (TPS27082LDDCR) will forward 3.3VIN voltage to 3.3V power rail.  The switch is enabled by the internal power good signal from DCDC which provides the internal core voltages. This complies with the Xilinx power up sequencing.  INIT_B Pin will be release with pullup on this 3.3V power rail which force the FPGA together with PROGRAM_B to boot from QSPI Flash (See UG470).  However, a too slow increase of the 3.3VIN voltage can result in the internal voltages being generated, but the 3.3V voltage is not yet sufficient for the QSPI flash, but high enough that the FPGA try to boot from QSPI flash. In this case QSPI flash access can failed.

The same can happens with TE0714 on VIN and 3.3V in case assembly version with VCCIO_0=3.3V is used.

Solution:

  1. Use input voltage power regulator with ramp time no more than 40ms (see ds181 Table 7: Power Supply Ramp Time)
  2. The "EN1" (power on) signal should turn on when VIN and 3.3VIN are stable and reach 90% of the target value.
  3. Trenz Electronic will  check on every module, if this issue can be prevent with PCB and or CPLD firmware modification on next PCB revision update



Contact Information

If you have any questions related to this PCN, please contact Trenz Electronics Technical Support at

Disclaimer

Any projected dates in this PCN are based on the most current product information at the time this PCN is being issued, but they may change due to unforeseen circumstances.  For the latest schedule and any other information, please contact your local Trenz Electronic sales office, technical support or local distributor.

This PCN follows JEDEC Standard J-STD-046.

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