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Firmware for PCB CPLD with designator U3: LCMX02-256HC

Feature Summary

  • JTAG Multiplexer
  • Module Power sequencing
  • FPGA Configuration sequencing
  • LED Status and User access
  • FPGA IO User access
  • I2C interface

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHDL NameDirectionPinPullup/DownBank PowerDescriptionNote: PCB REV03 ConnectionNote: PCB REV2 REV1 Connection
JTAGENin26---3.3VSwitch JTAG between CPLD and FPGA (logical one for CPLD, logical zero for FPGA)

TMS / TMSIN29DOWN3.3VJTAG from B2B connector

TCK / TCKIN30DOWN3.3VJTAG from B2B connector

TDI / TDIIN32DOWN3.3VJTAG from B2B connector

TDO / TDOOUT1DOWN3.3VJTAG from B2B connector





ULI_SYSTEM / ULI_SYSTEMIN4UP3.3VFPGA access W22 PIN / This pin is connected to internal clock of CPLD in CPLD firmware revision 1. / In CPLD firmware revision 2 is used as SCL pin of I2C interface between CPLD and FPGA.

FPGA_IOINOUT10UP3.3VFPGA access U22 PIN (PUDC) / This pin is connected to LED1 for CPLD firmware revision 1. / In CPLD firmware revision 2 and later is used as SDA pin of I2C interface between CPLD and FPGA after configuring the FPGA.

RESININ16UP3.3VRESETIN from B2B connector (Negative Reset)

DONEIN28UP3.3VFPGA Configuration DONE_0 Pin

PROG_BOUT27UP3.3VFPGA Configuration PROGRAM_B_0 Pin

PGOODOUT12UP3.3VPGOOD to B2B connector

PG_ALL / PG_ALLIN25UP3.3Vfrom module generated 3.3V VoltageAs PG_ALL renamed /In the hardware is connected to 3.3V./ In CPLD firmware is pulled up.As PG_SENSE in CPLD firmware code. / In the hardware is connected to 3.3V. (Without label)
EN1IN11UP3.3VPower Enable from B2B Connector (Positive Enable)



MODEINOUT13UP3.3VIn firmware revision 1 is unused. / For firmware revision 2 is used as GPIO for user.

NOSEQINOUT14UP3.3VIn firmware revision 1 is unused. / For firmware revision 2 is used as GPIO for user. 

ULI_CPLD / ULI_CPLDINOUT5NONE3.3VIn firmware revision 1 is unused. / For firmware revision 2 is connected to internal clock of CPLD.

Functional Description


JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA).


PGOOD is zero, if EN1 or PG_ALL is zero else high impedance state. PUDC is high during FPGA configuration.

FPGA Configuration

FPGA configuration process will be started, if RESIN, PG_ALL and EN1 is ONE.

I2C interface

CPLD firmware consists of a i2c t GPIO block. This subsystem provides i2c protocol interface to  32-bit (4 x 8-bit) (GPIO_input[31:0]) registers for reading from CPLD and (4 x 8-bit) (GPIO_output[31:0]) registers for writing in CPLD as general purpose parallel input and output (I/Os). The written and read data is communicated from/to FPGA via i2c bus interface protocol. The address of this block in the firmware is 0x20.In this case related i2c bus is bus 1. 

RegisterDirection in CPLDAddress
GPIO_input[7:0]Output (reading from CPLD)0x00
GPIO_input[15:8]Output (reading from CPLD)0x01
GPIO_input[23:16]Output (reading from CPLD)0x02
GPIO_input[31:24]Output (reading from CPLD)0x03
GPIO_output[7:0]Input (writing to CPLD)0x00
GPIO_output[15:8]Input (writing to CPLD)0x01
GPIO_output[23:16]Input (writing to CPLD)0x02
GPIO_output[31:24]Input (writing to CPLD)0x03


Noseq pin can be used by user as GPIO. In this case the following table is valid:

NOSEQ pin as outputConditionCommand in linux console
'1'GPIO_output(16) = '0'
i2cset -y 1 0x20 0x02 0x00
'0'GPIO_output(16) = '1'
i2cset -y 1 0x20 0x02 0x01
NOSEQ pin as inputDescriptionCommand in linux console
Reading state of NOSEQ pinGPIO_input(16) = NOSEQ
i2cget -y 1 0x20 0x02


Mode pin can read via I2C too:

MODE pinDescriptionCommand in linux console
Reading state of MODE pinGPIO_input(17) = MODE
i2cget -y 1 0x20 0x02


SYSLED1 (Green)Blink sequence ********RESIN = '0'
SYSLED1 (Green)Blink sequence ****ooooDONE = '0'
SYSLED1 (Green)ONGPIO_output(17) = '1'
Related command in linux console:   i2cset -y 1 0x20 0x02 0x02
SYSLED1 (Green)OFFotherwise
LEDSTATUSCondition (User defined)Description
SYSLED2 (Red)OFFMODE = '0' and NOSEQ = '0'

MODE can be changed for example for TE0703 carrier board via dip switch S2-4.
NOSEQ can be changed in linux console via i2cset command. 

SYSLED2 (Red)Blink sequence **ooooooMODE = '0' and NOSEQ = '1'NOSEQ can be set high via the following command in linux console:
i2cset -y 1 0x20 0x02 0x00
SYSLED2 (Red)Blink sequence *****oooMODE = '1' and NOSEQ = '0'MODE can be set high via setting MODE pin in carrier board. For example if you use TE0703 as carrier board MODE pin is connected with dip switch S2-4.
SYSLED2 (Red)ONMODE = '1' and NOSEQ = '1'

Access to CPLD registers

CPLD registers can be accessed via i2c interface. In the following table is shown how these registers can be read or written:

RegisterDirection in CPLDAddressRelated instruction in linux console to access the register
GPIO_input[7:0]Output (reading from CPLD)0x00
i2cget -y 1 0x20 0x00
GPIO_input[15:8]Output (reading from CPLD)0x01
i2cget -y 1 0x20 0x01
GPIO_input[23:16]Output (reading from CPLD)0x02
i2cget -y 1 0x20 0x02
GPIO_input[31:24]Output (reading from CPLD)0x03
i2cget -y 1 0x20 0x03
GPIO_output[7:0]Input (writing to CPLD)0x00
i2cset -y 1 0x20 0x00 <data>
GPIO_output[15:8]Input (writing to CPLD)0x01
i2cset -y 1 0x20 0x01 <data>
GPIO_output[23:16]Input (writing to CPLD)0x02
i2cset -y 1 0x20 0x02 <data>
GPIO_output[31:24]Input (writing to CPLD)0x03
i2cset -y 1 0x20 0x03 <data>

The first register GPIO_input[7:0] is used  to show CPLD revision.

RegisterAddressRelated dataRead/Write by userDescription
GPIO_input[7:0]0x00CPLD REVISION (8 bits)No
GPIO_input(16)0x02NOSEQ pinYes
To read NOSEQ pin : i2cget -y 1 0x20 0x02 --> Bit 0 shows NOSEQ pin state.
GPIO_input(17)0x02MODE pinYes
To read MODE pin : i2cget -y 1 0x20 0x02 --> Bit 1 shows MODE pin state.
RegisterAddressrelated data
GPIO_output(16)0x02NOSEQ pinYes
For example to set NOSEQ pin high: i2cset -y 1 0x20 0x02 0x00
GPIO_output(17)0x02SYSLED1 (Green)Yes
To turn SYSLED1 (Green) on : i2cset -y 1 0x20 0x02 0x02

The CPLD revision is displayed in linux console while booting as shown:

Showing CPLD revision

If CPLD firmware is older than REV02, then CPLD revision will not be displayed and user should update the firmware. In this case the following message will be displayed:

Updating CPLD firmware message

Appx. A: Change History

Revision Changes

REV02 to REV03 changes:

  • The state of FPGA_IO pin (PUDC pin) is set to high to measure the voltage of the FPGA IO pins correctly even if the FPGA is not programmed.

REV01 to REV02 changes:

  • Renaming the port signals according to the schematic.

  • Defining and reading CPLD Revision via i2c interface.

  • JTAG signal timing adjustment

  • Adding i2c to gpio ip (i2c_slave.vhd)

  • LEDs functions was changed:

    • SYSLED1 (green LED) shows the DONE and RESIN and GPIO_output(17) bit state of GPIO_output register.

    • SYSLED2 (Red LED) shows the state of NOSEQ and MODE pins.

  • PG_SENSE renamed to PG_ALL.
  • PGOOD pulled up.

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

 REV03 REV01, REV02, REV03
  • Firmware REV03 release
  • Firmware release (
  • The state of PUDC pin is set to high to measure the voltage of the FPGA IO pins correctly even if the FPGA is not programmed.
2022-10-20v.25REV02 REV01, REV02, REV03Mohsen Chamanbaz
  • Firmware REV02  release
  • Firmware release (
  • I2C interface between CPLD chip and FPGA added
  • Indicating CPLD revision while booting
2018-05-15v.24REV01 REV01, REV02John Hartfiel
  • document style update
  • add PUDC status



REV01, REV02
  • Rev01, Firmware released  2014-07-03


  • Initial release


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