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Key Features

  • EDDP with FOC algorithm designed in SDSoC for TE0701 carrier board.
  • Automated generation of SDSoC platforms for family of TE0720 modules.

Revision History

DateVivadoProject BuiltAuthorsDescription
2018-08-272017.1TE0701_zsys_SDSoC_EDDP_FOC-vivado_2017.1-build_05_20180827095945.zipUTIAinitial release

Release Notes and Know Issues

IssuesDescriptionWorkaroundTo be fixed version
No known issues---------





Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TE0720-03-2IFTE0720_2IFREV031 GB32

TE0720-03-l1if   TE0720_L1IF REV03512MB (L)32

TE0720-03-1CFTE0720_1CFREV031 GB32

TE0720-03-2EFTE0720_2EFREV031 GB32

TE0720-03-07STE0720_07SREV031 GB (L)32

Design supports following carriers:

Carrier ModelNotes

Additional HW Requirements:


For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration
SDSoC<design name>/../SDSoC_PFMSDSoC Platform will be generated by TE Scripts

Additional Sources



Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Hardware Setup

TE0701_zsys_SDSoC_EDDP_FOC  2017.1 platform with TEC0053 Power Stage

3-phase brush-less DC motor control with field oriented control (FOC) algorithm implemented in SDSoC 2017.1 on TE0720 module and TE0701-06 carrier board. The TEC0053-04 - EDPS Power Stage controls the BLDC Motor with mounted Encoder.

The following steps are describing how to connect and setup hardware parts shown in the Figure above.

  1. Set TE0701-06 carrier board FMC_VADJ = 3.3V by switch S4:


  2. Set FMC_VADJ (set in step 1 to 3.3V) to drive both, the VIOTA and VIOTB by this arrangement of J16, J17 and J21.

    J6Short 1-2
    J17no connection
    J21Short 2-3

    VIOTA will provide 3.3V to PMOD J5 and FMC_VADJ will provide 3.3V to PMOD J6

  3. Set switch S3  of the TE0701-06 carrier board to:


    S3_1 and S3_2 serve as general purpose pins connected to the CPLD on the TE0701-06.


    Before connecting to TEC0053-04 by PMOD 12pin cables, power on the  TE0701-06 (12V) and measure presence of the 3.3V voltage on the TE0701-06 PMOD J5 pin 12 and pin 6 and on the TE0701-06 PMOD J6 pin 12 and pin 6.

  4. Connect TEC0053 to two 3.3V PMOD connectors on TE0701 carrier with two 
    Pmod 12-pin cables as shown in following image.

  5. Connect of motor rotation encoder as shown in following figure

    Motor rotation encoder is connected to the TEC0053-04 - EDPS Power Stage Pmod 6 pin cable connector kit. See the orientation and position of the 5 wire connection. There are 6 pins on the TEC0053-04 board. There are only 5 pins on the motor encoder. Pin 1 connects to pin 1. 6-th wire is unconnected on the motor encoder side.   

    3-phase of the motor phases are connected to the TEC0053-04 - EDPS Power Stage points A, B and C:
    A: green wire; B: red wire; C: black wire.

    All other motor wires are unused.
    The  TEC0053-04 - EDPS Power Stage can be powered by 12 V  from the power supply by separate wire connecting of the point labled “PWR” (see above) with the fused point labled “+DC” (see the first picture).

    Description of connections of TE0701 with TEC0053-04
    # First PMOD cable 12-pin:
    # Connections of 					# TE0701-06 J5 		with TEC0053 J9    
    set_property PACKAGE_PIN W18 [get_ports {SDV}];    	#TE0701-06 J5:7 	with TEC0053 J9:7   
    set_property PACKAGE_PIN W17 [get_ports {ENC_A}];   #TE0701-06 J5:8 	with TEC0053 J9:8
    set_property PACKAGE_PIN Y19 [get_ports {ENC_B}];  	#TE0701-06 J5:9 	with TEC0053 J9:9
    set_property PACKAGE_PIN AA19 [get_ports {ENC_I}]; 	#TE0701-06 J5:10 	with TEC0053 J9:10
    # GND   											#TE0701-06 J5:11 	with TEC0053 J9:11
    # 3,3V   											#TE0701-06 J5:12 	with TEC0053 J9:12
    set_property PACKAGE_PIN Y16 [get_ports {SCLK}];   	#TE0701-06 J5:1 	with TEC0053 J9:1
    set_property PACKAGE_PIN W16 [get_ports {SDI1}];   	#TE0701-06 J5:2 	with TEC0053 J9:2
    set_property PACKAGE_PIN Y18 [get_ports {SDI2}];   	#TE0701-06 J5:3 	with TEC0053 J9:3
    set_property PACKAGE_PIN AA18 [get_ports {SDI3}];   #TE0701-06 J5:4 	with TEC0053 J9:4 
    #GND 												#TE0701-06 J5:5 	with TEC0053 J9:5 
    #3,3V 												#TE0701-06 J5:6 	with TEC0053 J9:6 
    #All signals connected by the first PMOD cable cable belong to TE0720 Zynq Bank 33. 
    # Second PMOD cable 12-pin: 
    # Connections of 									#TE0701-06 J6 		with TEC0053 J8
    set_property PACKAGE_PIN Y8 [get_ports {GL[0]}]; 	#TE0701-06 J6:7 	with TEC0053 J8:7 
    set_property PACKAGE_PIN Y9 [get_ports {GL[1]}]; 	#TE0701-06 J6:8 	with TEC0053 J8:8 
    set_property PACKAGE_PIN V9 [get_ports {GL[2]}]; 	#TE0701-06 J6:9 	with TEC0053 J8:9 
    #GND 												#TE0701-06 J6:11 	with TEC0053 J8:11 
    #3,3V 												#TE0701-06 J6:12 	with TEC0053 J8:12 
    set_property PACKAGE_PIN AA7 [get_ports {GH[0]}]; 	#TE0701-06 J6:1	 	with TEC0053 J8:1 
    set_property PACKAGE_PIN AA6 [get_ports {GH[1]}]; 	#TE0701-06 J6:2 	with TEC0053 J8:2 
    set_property PACKAGE_PIN U11 [get_ports {GH[2]}]; 	#TE0701-06 J6:3 	with TEC0053 J8:3 
    #GND 												#TE0701-06 J6:5 	with TEC0053 J8:5 
    #3,3V 												#TE0701-06 J6:6 	with TEC0053 J8:6 
    # Second PMOD Cable 12-pin contains these two wires unconnected to the SDSoC design: 
    #set_property PACKAGE_PIN V10 [get_ports {gpio_0_tri_io[0]}]; 	#TE0701-06 J6:10 - TEC0053 J8:10 
    #set_property PACKAGE_PIN U12 [get_ports {gpio_0_tri_io[1]}]; 	#TE0701-06 J6:4 - TEC0053 J8:4 
    #All signals connected by the second Pmod cable belong to TE0720 Zynq Bank 13. 

    Older Carrier Board Revisions

    The older TE0701-04 or TE0701-05 carrier boards can be used with the identical platform, but 
    the setup for generation of 3.3V on the PMOD J5 and PMOD J6 is different. There is no S4 switch and the FMC_VADJ = 3.3 V needs to be set by switch S3. Set switch S3 of the TE0701-04 or TE0701-05 carrier board to: S3_1 OFF; S3_2 ON; S3_3 ON; S3_4 OFF  
    Arrange jumpers J17 and J21:
    J17: [1,2,3] connect 1-2
    J21: [1,2,3] connect 2-3

    Fixed 3.3V will go to PMOD J5. FMC_VADJ will provide 3.3V to PMOD J6Before connecting to TEC0053-04 by PMOD 12pin cables, power on (12V) the  TE0701-04 or the TE0701-05 carrier board and measure presence of the 3.3V voltage on the TE0701-06 PMOD J5 pin 12 on pin 6 and presence of the 3.3V voltage coming from the adjustable FMC_VADJ on the TE0701-04 or TE0701-05 PMOD J6 pin 12 and pin 6.

Design Setup

Create SDSoC Platform from TE Reference Design

  1. Unzip Reference Design


    Do not change base folder name after extraction! The name must be:

  2. CD to the directory and run from win terminal:

    run from win terminal:
    reply to select an virtual drive name (example X): X
    reply: 0

    cd X:\zsys

    This is shortest possible path and directory name for building of the platform
    in windows (to respect the 260 character limitations.)


    Do not change the name of the directory /zsys
    It has to be identical to the shortest possible platform name “zsys”
    for the Zynq 7000 targets.

  3. Enable SDSOC, set install path of Xilinx tools, set your hardware assembly option in: "design_basic_settings.cmd" Select one of these supported modules (1,4,5,6,7):

    IDTE Module

    NOTE:  Selection 7 supports the TE0720-03-14S-1C module (xc7z014sclg484-1c device).

  4.  Create Reference Design: run "vivado_create_project_guimode.cmd"

  5. VIVADO:
    1. TCL-Console type: TE::hw_build_design -export_prebuilt

    2. Find hardware handoff file .hdf under prebuilt folder abd copy it to Ubuntu 16.04, with installed Petalinux 2017.1 SDK.


      Before petalinux project can be built, the executable rights must be set for these files:


      In Ubuntu 16.04, build Petalinux image image.ub and uboot u-boot.elf using Petalinux BSP provided under "os" folder and place new images to correct subfolder in prebuilt/os

    3. TCL-Console type: TE::sw_run_hsi
    4. TCL-Console type:TE::ADV::beta_util_sdsoc_project
      1. Vivado project will be permanently modified in this step by copying constrain files locally to project.


        If needed, recreate original project with batch file (step 4) to restore original Vivado project with externally linked constrains.

    5. Wait for project creation:
    6. SDSoC Platform is created in  
      1. Copy
        X: \SDSoC_PFM\<TE::SHORTDIR>\zsys
      2. Copy these two files from:
      3. Copy directory with all files from:
        X: \SDSoC_PFM\<TE::SHORTDIR>\zsys\src\
      4. Copy directory with all files from:
        X: \SDSoC_PFM\<TE::SHORTDIR>\zsys\sw\aarch32-linux\
        X: \SDSoC_PFM\<TE::SHORTDIR>\zsys\sw\ aarch32-none\
    7. Close current Vivado project
    8. Clear working project files by script
    9. From win terminal, execute:
      reply to select an virtual drive name (example X): X
      reply: 1
      This will disconnect the virtual X: drive
    10. Compile support libraries serving for connection to 64bit AXI I/O.
    11. Open the SDx Terminal 2017.1
      1. CD to: <install_path>\TE0701_zsys_SDSoC_EDDP_FOC\SDSoC_PFM\<TE::SHORTDIR>\zsys\src\
      2. In the SDx Terminal 2017.1, run batch file:
      3. Library for the SDSoC Linux target is created:
      4. Move the created library libte0720_foc.a to
      5. Delete the created _sds directory
      6. In the SDx Terminal 2017.1, run batch file:
      7. Library for the SDSoC standalone target is created:
      8. Move the created library libte0720_foc.a to
        <install_path>\TE0701_zsys_SDSoC_EDDP_FOC\SDSoC_PFM\<TE::SHORTDIR>\zsys\sw\aarch32-none\lib\ libte0720_foc.a 
      9. Delete the created _sds directory
      10. The SDSoC platform for the target \<TE::SHORTDIR> is in
      11. Close the SDx Terminal 2017.1 

Set TE SDSoC Platform as local SDSoC Platform

  1. Use the created SDSoC Platform for <TE::SHORTDIR> module present in the directory:
    Open new windows terminal and CD to:
    1. From win terminal, run
      reply to select an virtual drive name (example X): X
      reply: 0
      CD to:
      This is shortest possible path and directory name for the SDSoC project working with the created SDSoC 2017.1 platform in the directory:

Create and Build SDSoC Project

  1. Start SDSoC 2017.1 in the directory
  2. Select Workspace

    X:\ <TE::SHORTDIR>
  3. Click "Create SDSoC Project"
    1. Set Project Name (example: foc01)
    2. Set Platform:
      1. Others. Path to Project is:
        X:\ <TE::SHORTDIR>\zsys
    3. Select OS: Linux
    4. Click "Next"
    5. Select Template Application "focserver"  "Field Oriented Control with Web UI"
    6. Click "Finished"
    7. Right click on the project -> C/C++ Build Settings
      In the top level Configuration menu select [All configurations]
    8. Add libraries 'te0720_foc' and 'dl' to the linker flags! -> SDS++ Linker -> Libraries
    9. Add path to directory with Linux version of the 'libte0720_foc.a' library! -> SDS++ Linker -> Libraries
      Example for <TE::SHORTDIR> = te0720_2if:
    10. Add path to directory with te0720_foc.h! -> SDSCC Compiler -> Directories
      Example for <TE::SHORTDIR> = te0720_2if:
    11. Add path to directory with te0720_foc.h! -> SDS++ Compiler -> Directories
      Example for <TE::SHORTDIR> = te0720_2if:
    12. In main SDx Project Settings:
      unselect box [] Generate bitstream
      unselect box [] Generate SD card image

      these two un-selections will accelerate the initial compilation of the platform, needed for creation of the final platform hdf file needed for generation of the final image.ub in the Petalinux 2017.1 under the Ubuntu. (cca 3 min instead of 20 min with these options selected).

      The .hdf description of the foc01 HW design and related drivers is created in file (Example for <TE::SHORTDIR> = te0720_2if):

    13. Copy created file zsys.hdf to Petalinux 2017.1 in Ubuntu 16.04 and recompile the configuration of Petalinux with this .hdf file.

      Result of this compilation is updated image.ub which includes device tree with the AXI-lite driver, created by the SDSoC initial compilation step. This driver is used by the focserver to set parameters of the HW accelerated SDSoC implementation of the FOC algorithm.
    14. Replace the initial image.ub of the SDSoC platform with the created final image.ub by copy to (Example for <TE::SHORTDIR> = te0720_2if):
    15. In SDSoC, clear the foc01 project.
    16. In main SDx Project Settings:
      select box [x] Generate bitstream
      select box [x] Generate SD card image
    17. Select Build project foc01
      The SDSoC project is recompiled (cca 20 min) with foc01 integrated in HW.
      SDCard image is created


  1. Copy created files to the SD card.
  2. ON PC, set the Ethernet address to
  3. Connect PC with Ethernet cable to the TE0701 board.
  4. Connect serial terminal via the USB cable.
  5. Power ON TEC0053-04 - EDPS Power Stage (12V).
  6. Power ON TE0701 board (12V).
  7. On PC, open serial terminal.
  8. Reset TE0701 board (by S2 button).
  9. Boot of Linux starts up to login stage. Login as 'root' with password 'root'.
    To see top running processes, type 
    you can see running process
  10. On PC, open www browser and connect to
    to connect to the focserver running on the TE0720 module.
  11. Use the GUI to start and control the BLDC motor and to visualize data.     


  • SDSoC Environment - User Guide (UG1027)
  • SDSoC Environment User Guide - An Instruction to SDSoC Environment (UG1028)
  • SDSoC Environment User Guide - Platforms and Libraries (UG1146)
  • EDDP Resources - Sources and documentation of the original EDDP Development kit

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionAuthorsDescription


  • update download

  • 2017.1 release
  • Initial release


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