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Table of contents

Overview

Key Features

  • EDDP with FOC algorithm designed in SDSoC for TE0706 carrier board.
  • Automated generation of SDSoC platforms for family of TE0720 modules.

Revision History

DateVivadoProject BuiltAuthorsDescription
2018-08-272017.1TE0706_zsys_SDSoC_EDDP_FOC-vivado_2017.1-build_05_20180827095117.zipUTIAinitial release

Release Notes and Know Issues

IssuesDescriptionWorkaroundTo be fixed version
No known issues---------

Requirements

Software

SoftwareVersionNote
PetaLinux2017.1needed
SDx2017.1needed

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TE0720-03-2IFTE0720_2IFREV031 GB32

TE0720-03-l1if   TE0720_L1IF REV03512MB (L)32

TE0720-03-1CFTE0720_1CFREV031 GB32

TE0720-03-2EFTE0720_2EFREV031 GB32

TE0720-03-07STE0720_07SREV031 GB (L)32

Design supports following carriers:

Carrier ModelNotes
TE0706-2

Additional HW Requirements:

Content

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration
SDSoC<design name>/../SDSoC_PFMSDSoC Platform will be generated by TE Scripts

Additional Sources

TypeLocationNotes




Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

Hardware Setup

TE0706_zsys_SDSoC_EDDP_FOC 2017.1 Platform with TEC0053-04 - EDPS Power Stage

3-phase brush-less DC motor control with field oriented control (FOC) algorithm implemented in SDSoC 2017.1 on TE0720 module and TE0706-02 carrier board. The TEC0053-04 - EDPS Power Stage controls the BLDC motor with mounted encoder.

How to setup hardware shown in the figure above is described in following steps:

  1. On TE0706-02 carrier board, use jumpers  J10, J11 and J12 to select 3.3V:


    JumperSettings
    J10Short 2-3
    J11Short 2-3
    J12Short 2-3



  2. On TE0706-02 carrier board,  set switch S1 to:

    SwitchSettings
    S1_1OFF
    S1_2OFF
    S1_3OFF
    S1_4ON
  3. On TE0790-02  XMOD FTDI JTAG Adapter of the TE0706-02 board, set switch S2 to:

    SwitchSettings
    S2_1ON
    S2_2OFF
    S2_3ON
    S2_4OFF



    IMPORTANT

    Before connecting to TEC0053-04 by PMOD 12pin cables, power on the TE0706-02 (NOTE: 5V!) and measure presence of 3.3V voltage on the TE0706-02  connector J5 pins: J5:5, J5:6, J5:45, J5:46. 

  4. Connection of motor rotation encoder




    Motor rotation encoder is connected to the TEC0053-04 - EDPS Power Stage Pmod 6 pin cable connector kit. See the orientation and position of the 5 wire connection. There are 6 pins on the TEC0053-04 board. There are only 5 pins on the motor encoder. Pin 1 connects to pin 1. 6-th wire is unconnected on the motor encoder side.   

    3-phase of the motor phase wires are connected to the TEC0053-04 Power Stage points A, B, C: A: green wire; B: red wire; C: black wire.
    All other motor wires are unused.

    The  TEC0053-04 - EDPS Power Stage can be powered by 12 V  from the power supply by separate wire connecting of the point labled “PWR” (see above) with the fused point labeled “+DC” (see the first picture). 

  5. Connect TE0706 with TEC0053-04 by two PMOD 12-pin cables.




    Description of connections of TE0706 with TEC0053-04
    # First 12 pin PMOD cable
    # Connections of TEC0053 J17 with TE0706-02 J5     		# TEC0053 	# TE0706-02
    # GND   												# J17:25	# J5:50
    set_property PACKAGE_PIN G20 [get_ports {SCLK}];  		# J17:23 	# J5:48 
    # 3,3V   												# J17:21 	# J5:46
    set_property PACKAGE_PIN E21 [get_ports {SDI1}];  		# J17:19 	# J5:44
    set_property PACKAGE_PIN B19 [get_ports {SDI2}];  		# J17:17 	# J5:42
    set_property PACKAGE_PIN D20 [get_ports {SDI3}];  		# J17:15 	# J5:40
    # GND   												# J17:26	# J5:49
    set_property PACKAGE_PIN G21 [get_ports {SDV}];   		# J17:24 	# J5:47
    # 3,3V   												# J17:22 	# J5:45
    set_property PACKAGE_PIN D21 [get_ports {ENC_A}]; 		# J17:20 	# J5:43 
    set_property PACKAGE_PIN B20 [get_ports {ENC_B}]; 		# J17:18 	# J5:41 
    set_property PACKAGE_PIN C20 [get_ports {ENC_I}]; 		# J17:16 	# J5:39 
    # All signals connected by the first PMOD cable cable belong to TE0720 Zynq Bank 35.
    # Second 12 pin PMOD cable
    # Connections of TEC0053 J17 with TE0706-02 J5     		# TEC0053 	# TE0706-02
    # GND   												# J17:1		# J5:2
    # Not used in the design								# J17:3 		# J5:4
    # 3,3V   												# J17:5 		# J5:6
    set_property PACKAGE_PIN W17 [get_ports {GH[2]}];  		# J17:7   	# J5:8
    set_property PACKAGE_PIN W20 [get_ports {GH[1]}];  		# J17:9   	# J5:10
    set_property PACKAGE_PIN AA16 [get_ports {GH[0]}]; 		# J17:11  	# J5:12
    # GND   												# J17:2		# J5:1
    # Not used in the design								# J17:4 		# J5:3
    # 3,3V   												# J17:6 		# J5:5
    set_property PACKAGE_PIN W18 [get_ports {GL[2]}];  		# J17:8   	# J5:7 
    set_property PACKAGE_PIN W21 [get_ports {GL[1]}];  		# J17:10  	# J5:9 
    set_property PACKAGE_PIN AB16 [get_ports {GL[0]}]; 		# J17:12  	# J5:11
    #All signals connected by the second PMOD cable belong to TE0720 Zynq Bank 33.
    # Second PMOD Cable 12-pin contains these two wires unconnected to the SDSoC design:
    # Unused connections of TEC0053 J17 with TE0706-02 J5     		# TEC0053 	# TE0706-02
    #set_property PACKAGE_PIN W16 [get_ports {gpio_0_tri_io[1]}]; 	# J17:3 	# J5:4
    #set_property PACKAGE_PIN Y16 [get_ports {gpio_0_tri_io[0]}];   # J17:4  	#J5:3 
    
    
    



    TE0706-02 carrier board has highlighted position of two 12 pin PMOD cables. Please take care, when connecting both cables to respect pin connections as listed above.


    TEC0053-04 power stage board has highlighted position of two 12 pin PMOD cables. 

    IMPORTANT

    Wrong placement of the PMOD 12pin connects might result in a damaged electronic. 



Design Setup

Create SDSoC Platform from TE Reference Design

  1. Unzip Reference Design
    1. Do not change base folder name after extraction!
      <install_path>\TE0706_zsys_SDSoC_EDDP_FOC\zsys\
      CD to the directory and run from win terminal:
      _create_win_setup.cmd

      run from win terminal:
      _use_virtual_drive.cmd
      reply to select an virtual drive name (example X): X
      reply: 0

      cd X:\zsys

      This is shortest possible path and directory name for building of the platform
      in windows (to respect the 260 character limitations.)

      NOTE

      Do not change the name of the directory /zsys
      It has to be identical to the shortest possible platform name “zsys”
      for the Zynq 7000 targets.



  2. Enable SDSOC, set install path of Xilinx tools, set your hardware assembly option in: "design_basic_settings.cmd" Select one of these supported modules (1,4,5,6,7):


    IDTE Module
    1te0720-03-2if
    4te0720-03-l1if
    5te0720-03-1cf
    6te0720-03-2ef
    7te0720-03-07s



    NOTE

    Selection 7 supports the TE0720-03-14S-1C module (xc7z014sclg484-1c device).



  3. Create Reference Design: run "vivado_create_project_guimode.cmd"

  4. VIVADO:

    1. TCL-Console type: TE::hw_build_design -export_prebuilt

    2. Find hardware handoff file .hdf under prebuilt folder abd copy it to Ubuntu 16.4,  with Petalinux 2017.1.

      IMPORTANT

      The executable flag under Linux OS must be set for files:


      ./init_config.sh
      ./project-spec/meta-user/recipes-apps/libuv/files/checksparse.sh
      ./project-spec/meta-user/recipes-apps/libuv/files/gyp_uv.py
      ./project-spec/meta-user/recipes-apps/libuv/files/autogen.sh
      ./project-spec/meta-user/recipes-apps/libuv/files/android-configure
      ./project-spec/meta-user/recipes-apps/libuv/update-src.sh



      In Ubuntu 16.04, build Petalinux image image.ub and uboot u-boot.elf using Petalinux BSP provided under os folder and place new images to correct subfolder in prebuilt/os


    3. TCL-Console type: TE::sw_run_hsi
    4. TCL-Console type:TE::ADV::beta_util_sdsoc_project
      1. Vivado project will be modified by copying constrain files locally to project.

        NOTE

        If needed, recreate project with batch file to restore original Vivado project with externally linked constrains.



    5. Wait for project creation: 

      1. SDSoC Platform is created in  
        X:\zsys\SDSoC_PFM\<TE::SHORTDIR>\zsys

      2. Copy
        X:\zsys\_use_virtual_drive.cmd
        to 
        X: \SDSoC_PFM\<TE::SHORTDIR>\zsys

      3. Copy these two files from:
        X:\zsys\init.sh
        X:\zsys\focserver.conf
        to
        X:\SDSoC_PFM\<TE::SHORTDIR>\zsys\sw\linux\image\init.sh
        X:\SDSoC_PFM\<TE::SHORTDIR>\zsys\sw\linux\image\focserver.conf

      4. Copy directory with all files from:
        X:\zsys\misc\src\
        to
        X: \SDSoC_PFM\<TE::SHORTDIR>\zsys\src\

      5. v. Copy directory with all files from:
        X:\zsys\misc\sw\aarch32-linux\
        X:\zsys\misc\sw\aarch32-none\
        to
        X: \SDSoC_PFM\<TE::SHORTDIR>\zsys\sw\aarch32-linux\
        X: \SDSoC_PFM\<TE::SHORTDIR>\zsys\sw\ aarch32-none\

    6. Close current Vivado project
    7. Clear working project files by script
      X:\zsys\design_clear_design_folders.cmd

    8. From win terminal, execute:
      _use_virtual_drive.cmd
      reply to select an virtual drive name (example X): X
      reply: 1
      This will disconnect the virtual X: drive

    9. Compile support libraries serving for connection to 64bit AXI I/O.
      Open the SDx Terminal 2017.1
      CD to: <install_path>\TE0706_zsys_SDSoC_EDDP_FOC\SDSoC_PFM\<TE::SHORTDIR>\zsys\src\
      In the SDx Terminal 2017.1, run batch file:
      build_linux.bat
      Library for the SDSoC Linux target is created:
      <install_path>\TE0706_zsys_SDSoC_EDDP_FOC\SDSoC_PFM\<TE::SHORTDIR>\zsys\src\libte0720_foc.a
      Move the created library libte0720_foc.a to
      c:\TV71u\TE0706_zsys_SDSoC_EDDP_FOC\SDSoC_PFM\te0720_2if\zsys\sw\aarch32-linux\lib\libte0720_foc.a
      Delete the created _sds directory
      <install_path>\TE0706_zsys_SDSoC_EDDP_FOC\SDSoC_PFM\<TE::SHORTDIR>\zsys\src\_sds

      In the SDx Terminal 2017.1, run batch file:
      build_standalone.bat
      Library for the SDSoC standalone target is created:
      <install_path>\TE0706_zsys_SDSoC_EDDP_FOC\SDSoC_PFM\<TE::SHORTDIR>\zsys\src\libte0720_foc.a
      Move the created library libte0720_foc.a to
      <install_path>\TE0706_zsys_SDSoC_EDDP_FOC\SDSoC_PFM\<TE::SHORTDIR>\\zsys\sw\aarch32-none\lib\ libte0720_foc.a
      Delete the created _sds directory
      <install_path>\TE0706_zsys_SDSoC_EDDP_FOC\SDSoC_PFM\<TE::SHORTDIR>\zsys\src\_sds
      The SDSoC platform for the target \<TE::SHORTDIR> is in
      <install_path>\TE0706_zsys_SDSoC_EDDP_FOC\SDSoC_PFM\<TE::SHORTDIR>

      Close the SDx Terminal 2017.1

Set TE SDSoC Platform as local SDSoC Platform

  1. Use the created SDSoC Platform for <TE::SHORTDIR> module present in the directory:
    Open new windows terminal and CD to:

    <install_path>\TE0706_zsys_SDSoC_EDDP_FOC\SDSoC_PFM\<TE::SHORTDIR>
    1. From win terminal, run
      _use_virtual_drive.cmd
      reply to select an virtual drive name (example X): X
      reply: 0
      CD to:
      X:\<TE::SHORTDIR>
      This is shortest possible path and directory name for the SDSoC project working with the created SDSoC 2017.1 platform in the directory:
      X:\<TE::SHORTDIR>\zsys

Create SDSoC Project

  1. Start SDSoC 2017.1 in the directory
  2. Select Workspace

    X:\ <TE::SHORTDIR>
  3. Click "Create SDSoC Project"
    1. Set Project Name (example: foc01)
    2. Set Platform:
      1. Others. Path to Project is:
        X:\ <TE::SHORTDIR>\zsys
    3. Select OS: Linux
    4. Click "Next"
    5. Select Template Application "focserver"  "Field Oriented Control with Web UI"
    6. Click "Finished"
    7. Right click on the project -> C/C++ Build Settings
      In the top level Configuration menu select [All configurations]
    8. Add libraries 'te0720_foc' and 'dl' to the linker flags! -> SDS++ Linker -> Libraries
    9. Add path to directory with Linux version of the 'libte0720_foc.a' library! -> SDS++ Linker -> Libraries
      Example for <TE::SHORTDIR> = te0720_2if:
      "X:/te0720_2if/zsys/sw/aarch32-linux/lib"
    10. Add path to directory with te0720_foc.h! -> SDSCC Compiler -> Directories
      Example for <TE::SHORTDIR> = te0720_2if:
      "X:/te0720_2if/zsys/sw/aarch32-linux/include"
    11. Add path to directory with te0720_foc.h! -> SDS++ Compiler -> Directories
      Example for <TE::SHORTDIR> = te0720_2if:
      "X:/te0720_2if/zsys/sw/aarch32-linux/include"
    12. In main SDx Project Settings:
      unselect box [] Generate bitstream
      unselect box [] Generate SD card image

      these two unselections will accelerate the initial compilation of the platform, needed for creation of the final platform hdf file needed for generation of the final image.ub in the Petalinux 2017.1 under the Ubuntu. (cca 4 min instead of 30 min with these options selected).

      The .hdf description of the foc01 HW design and related drivers is created in file (Example for <TE::SHORTDIR> = te0720_2if):

      X:\te0720_2if\foc01\Debug\_sds\p0\ipi\zsys.sdk\zsys.hdf  
    13. Copy created file zsys.hdf to Petalinux 2017.1 in Ubuntu 16.04 and recompile the configuration of Petalinux with this .hdf file.

      Result of this compilation is updated image.ub which includes device tree with the AXI-lite driver, created by the SDSoC initial compilation step. This driver is used by the focserver to set parameters of the HW accelerated SDSoC implementation of the FOC algorithm.
    14. Replace the initial image.ub of the SDSoC platform with the created final image.ub by copy to (Example for <TE::SHORTDIR> = te0720_2if):
      X:\te0720_2if\zsys\sw\linux\image\image.ub
    15. In SDSoC, clear the foc01 project.
    16. In main SDx Project Settings:
      select box [x] Generate bitstream
      select box [x] Generate SD card image
    17. Select Build project foc01
      The SDSoC project is recompiled (cca 30 min) with foc01 integrated in HW.
      SDCard image is created

Launch

  1. Copy created files to the SD card.
  2. ON PC, set the Ethernet address to 192.168.42.100
  3. Connect PC with Ethernet cable to the TE0706 board.
  4. Connect serial terminal via the USB cable.
  5. Power ON TEC0053-04 - EDPS Power Stage (12V).
  6. Power ON TE0706 board (12V).
  7. On PC, open serial terminal.
  8. Reset TE0705 board (by S2 button).
  9. Boot of Linux starts up to login stage. Login as 'root' with password 'root'.
    To see top running processes, type 
    top
    you can see running process
    focserver
  10. On PC, open www browser and connect to 
    http://192.168.42.123
    to connect to the focserver running on the TE0720 module.
  11. Use the WWW GUI to start and control the BLDC motor and to visualize data.     

References


  • SDSoC Environment - User Guide (UG1027)
  • SDSoC Environment User Guide - An Instruction to SDSoC Environment (UG1028)
  • SDSoC Environment User Guide - Platforms and Libraries (UG1146)
  • EDDP Resources - Sources and documentation of the original EDDP Development kit

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionAuthorsDescription

v.8

  • update download

v.7UTIA
  • 2017.1 release
2018-08-15v.1
  • Initial release

All

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