Table of contents
Firmware for PCB CPLD with designator U7. CPLD Device in Chain: LCMX02-256HC
- Power Monitoring
Firmware Revision and supported PCB Revision
See Document Change History
|Name / opt. VHD Name||Direction||Pin||Bank Power||Description|
|C_LED / LED1||out||17||3.3V||Green LED D4|
|DONE||in||28||3.3V||FPGA Done signal|
|F_TCK / C_TCK||out||9||3.3V||FPGA JTAG|
|F_TDI / C_TDI||out||21||3.3V||FPGA JTAG|
|F_TDO / C_TDO||in||5||3.3V||FPGA JTAG|
|F_TMS / C_TMS||out||4||3.3V||FPGA JTAG|
|GND||14||3.3V||connected to GND|
|JTAGMODE||26||3.3V||Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access)|
|PG_ALL||in||27||3.3V||Power sense from 1.8V/3.3V|
|PGOOD||inout||25||3.3V||Power Good. Low, if power failed, internal pullup activated|
|RESIN||in||8||3.3V||external reset from B2B|
|TCK / M_TCK||in||30||3.3V||B2B JTAG|
|TDI / M_TDI||in||32||3.3V||B2B JTAG|
|TDO / M_TDO||out||1||3.3V||B2B JTAG|
|TMS / M_TMS||in||29||3.3V||B2B JTAG|
|XIO||out||20||3.3V||FPGA IO from Bank14 H26 / 24.18MHz CLK from CPLD internal Osc.|
JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on JM1-89.
PROG_B is RESIN and PG_ALL.
PG_ALL is used for PROG_B Reset and LED.
PGOOD is set low, if PG_ALL failed otherwise high impedance. Internal pullup is activated.
PGOOD can be drive to low from carrier, this will be indicated by LED subsequency only.
|LED D4 Green|
|Reset||********||1||external Reset is set|
|Power failed||*****ooo||2||PG_ALL Problem (1.8V or 3.3V)|
|PGOOD Low||****oooo||3||PGOOD is set low from carrier|
|DONE||*ooooooo||4||Module not programmed|
|Ready||OFF||5||Module ready and programmed|
Appx. A: Change History and Legal Notices
CPLD REV01 to REV02
- add PGOOD functionality
- new LED status sequence
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
|Date||Document Revision||CPLD Firmware Revision||Supported PCB Revision||Authors||Description|
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