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Table of Contents

Overview

The Trenz Electronic TE0783 is a high-performance, industrial-grade SoM (System on Module) with industrial temperature range based on Xilinx Zynq-7000 SoC (XC7Z035, XC7Z045 or XC7Z100).

These highly integrated modules with an economical price-performance-ratio have a form-factor of 8,5 x 8,5 cm and are available in several versions.

All parts cover at least industrial temperature range of -40°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options and for modified PCB-equipping due increasing cost-performance-ratio and prices for large-scale order.

Key Features

  • Xilinx Zynq-7000 XC7Z045-2FFG900I SoC
  • Rugged for shock and high vibration
  • Large number of configurable I/Os are provided via rugged high-speed stacking strips
  • Dual ARM Cortex-A9 MPCore
    • 1 GByte RAM (32bit wide DDR3) connected to PS
    • 2 GByte RAM (64bit wide DDR3) connected to PL
    • 32 MByte QSPI Flash memory
    • Hi-Speed USB2 ULPI transceiver PHY
    • Gigabit (10/100/1000 Mbps) Ethernet transceiver PHY
    • 4 GByte eMMC (optional up to 64 GByte)
  • Lattice MachXO2 HC 4000 System Controller CPLD
    • 40 GPIO's available to user on B2B connector
  • MAC-address EEPROM
  • Serial user EEPROM
  • Temperature compensated RTC (real-time clock)
  • Si5338A programmable quad PLL clock generator for GTX transceiver clocks
  • Plug-on module with 3 x 160-pin high-speed strips
    • 16 GTX high-performance transceiver
    • 4x GT transceiver clock inputs
    • 166 FPGA I/O's (83 LVDS pairs)
  • On-board high-efficiency switch-mode DC-DC converters
  • System management
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Evenly-spread supply pins for good signal integrity
  • User LED

Assembly options for cost or performance optimization available upon request.


Additional assembly options are available for cost or performance optimization upon request.

Block Diagram

Figure 1: TE0783-01 block diagram

Main Components

Figure 2: TE0783-01 main components


  1. Xilinx Zynq-7000 SoC, U1
  2. 4Gbit DDR3L SDRAM, U19
  3. 4Gbit DDR3L SDRAM, U10
  4. 4Gbit DDR3L SDRAM, U8
  5. 4Gbit DDR3L SDRAM, U9
  6. 4Gbit DDR3L SDRAM, U14
  7. 4Gbit DDR3L SDRAM, U12
  8. SI5338A programmable quad PLL clock generator, U2
  9. SiTime SiT8008 25.000000 MHz oscillator, U3
  10. Lattice Semiconductor MachXO2 4000HC CPLD, U32
  11. Microchip 128Kbit I²C EEPROM, U26
  12. Microchip 2Kbit I²C MAC EEPROM, U22
  13. TPS780180300 LDO @1.8V backup battery voltage, U21
  14. TCA9406DCUR I²C voltage level shifter, U25
  15. Intersil ISL12020MIRZ Real Time Clock, U17
  16. Microchip USB3320C USB PHY transceiver, U4
  17. SiTime SiT8008 52.000000 MHz oscillator, U7
  18. 74AVCH4T245 voltage level tranlator, U30
  19. TPS74801RGW LDO @1.5V, U23
  20. 32 MByte QSPI Flash memory, U38
  21. LT quad 4A PowerSoC DC-DC converter (@1.0V), U13
  22. LT quad 4A PowerSoC DC-DC converter (@3.3V, @1,8V, @1.2V_MGT, @1.0V_MGT), U16
  23. TPS74801RGW LDO @1.5V_PL, U20
  24. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J2
  25. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J3
  26. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J1
  27. Micron Technology 4 GByte eMMC, U28
  28. Marvell Alaska 88E1512 Gigabit Ethernet PHY, U18
  29. Texas Instruments TXS02612RTWR SDIO Port Expander, U29
  30. SiTime SiT8008 25.000000 MHz oscillator, U11
  31. DSC1123CI2 Low-Jitter Precision LVDS Oscillator, U31
  32. SiTime SiT8008 33.333333 MHz oscillator, U33
  33. TPS799 LDO @1.8V_MGT, U5
  34. TPS799 LDO @VCCAUX_IO (1.8V), U35

Initial Delivery State

Storage device nameContentNotes
24LC128-I/ST EEPROMnot programmedUser content

24AA025E48 EEPROM

User content not programmed

Valid MAC Address from manufacturer
Si5338A OTP Areanot programmed-
eMMC Flash MemoryEmpty, not programmedExcept serial number programmed by flash vendor

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor

SPI Flash Quad Enable bit

Programmed

-

SPI Flash main array

demo design

-

eFUSE USER

Not programmed

-

eFUSE Security

Not programmed

-

Table 1: Initial delivery state of programmable devices on the module

Boot Process

6 of the 7 boot mode strapping pins (MIO2 ... MIO8) of the Xilinx Zynq-7000 SoC device are hardware programmed on the board, 1 of them is set by the SC CPLD firmware. The boot strapping pins are evaluated by the Zynq device soon after the 'PS_POR' signal is deasserted to begin the boot process (see section "Boot Mode Pin Settings" of Xilinx manual UG585).

The TE0783 boot mode is selected by the pin 'CPLD_GPIO3' of the SC CPLD, which is connected to B2B pin J2-16 to either boot from the on-board QSPI Flash memory U38 or SD IO interface. See section Bootmode in the TE0783 SC CPLD reference Wiki page.

The JTAG interface of the module is provided for storing the data to the QSPI Flash memory through the Zynq-7000 device.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

Zynq-7000 SoC's I/O banks signals connected to the B2B connectors:

BankType

B2B Connector

I/O Signal Count

DifferentialVoltageNotes
9HRJ2213.3Vfixed bank voltage to 3.3V

10

HR

J3

44

22

User

Max voltage 3.3V

11

HR

J3

40

20

User

Max voltage 3.3V
12

HR

J2

40

20

User

Max voltage 3.3V

13

HR

J2

40

20

User

Max voltage 3.3V

Table 2: General overview of board to board I/O signals

For detailed information about the pin-out, please refer to the Pin-out table.

MGT Lanes

The Xilinx Zynq-7000 SoC used on the TE0783 module has 16 MGT transceiver lanes. All of them are wired directly to B2B connectors J1 and J3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane with data transmission rates up to 12.5Gb/s per lane (Xilinx GTX transceiver). Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

BankTypeLaneSignal NameB2B PinFPGA Pin
109GTX0
  • MGT_RX0_P
  • MGT_RX0_N
  • MGT_TX0_P
  • MGT_TX0_N
  • J3-32
  • J3-30
  • J3-31
  • J3-29
  • MGTXRXP0_109
  • MGTXRXN0_109
  • MGTXTXP0_109
  • MGTXTXN0_109
1
  • MGT_RX1_P
  • MGT_RX1_N
  • MGT_TX1_P
  • MGT_TX1_N
  • J3-28
  • J3-26
  • J3-27
  • J3-25
  • MGTXRXP1_109
  • MGTXRXN1_109
  • MGTXTXP1_109
  • MGTXTXN1_109
2
  • MGT_RX2_P
  • MGT_RX2_N
  • MGT_TX2_P
  • MGT_TX2_N
  • J3-24
  • J3-22
  • J3-23
  • J3-21
  • MGTXRXP2_109
  • MGTXRXN2_109
  • MGTXTXP2_109
  • MGTXTXN2_109
3
  • MGT_RX3_P
  • MGT_RX3_N
  • MGT_TX3_P
  • MGT_TX3_N
  • J3-20
  • J3-18
  • J3-19
  • J3-17
  • MGTXRXP3_109
  • MGTXRXN3_109
  • MGTXTXP3_109
  • MGTXTXN3_109
110GTX0
  • MGT_RX4_P
  • MGT_RX4_N
  • MGT_TX4_P
  • MGT_TX4_N
  • J3-16
  • J3-14
  • J3-15
  • J3-13
  • MGTXRXP0_110
  • MGTXRXN0_110
  • MGTXTXP0_110
  • MGTXTXN0_110
1
  • MGT_RX5_P
  • MGT_RX5_N
  • MGT_TX5_P
  • MGT_TX5_N
  • J3-12
  • J3-10
  • J3-11
  • J3-9
  • MGTXRXP1_110
  • MGTXRXN1_110
  • MGTXTXP1_110
  • MGTXTXN1_110
2
  • MGT_RX6_P
  • MGT_RX6_N
  • MGT_TX6_P
  • MGT_TX6_N
  • J3-8
  • J3-6
  • J3-7
  • J3-5
  • MGTXRXP2_110
  • MGTXRXN2_110
  • MGTXTXP2_110
  • MGTXTXN2_110
3
  • MGT_RX7_P
  • MGT_RX7_N
  • MGT_TX7_P
  • MGT_TX7_N
  • J3-4
  • J3-2
  • J3-3
  • J3-1
  • MGTXRXP3_110
  • MGTXRXN3_110
  • MGTXTXP3_110
  • MGTXTXN3_110
111GTX0
  • MGT_RX8_P
  • MGT_RX8_N
  • MGT_TX8_P
  • MGT_TX8_N
  • J1-1
  • J1-3
  • J1-2
  • J1-4
  • MGTXRXP0_111
  • MGTXRXN0_111
  • MGTXTXP0_111
  • MGTXTXN0_111
1
  • MGT_RX9_P
  • MGT_RX9_N
  • MGT_TX9_P
  • MGT_TX9_N
  • J1-5
  • J1-7
  • J1-6
  • J1-8
  • MGTXRXP1_111
  • MGTXRXN1_111
  • MGTXTXP1_111
  • MGTXTXN1_111
2
  • MGT_RX10_P
  • MGT_RX10_N
  • MGT_TX10_P
  • MGT_TX10_N
  • J1-9
  • J1-11
  • J1-10
  • J1-12
  • MGTXRXP2_111
  • MGTXRXN2_111
  • MGTXTXP2_111
  • MGTXTXN2_111
3
  • MGT_RX11_P
  • MGT_RX11_N
  • MGT_TX11_P
  • MGT_TX11_N
  • J1-13
  • J1-15
  • J1-14
  • J1-16
  • MGTXRXP3_111
  • MGTXRXN3_111
  • MGTXTXP3_111
  • MGTXTXN3_111
112GTX0
  • MGT_RX12_P
  • MGT_RX12_N
  • MGT_TX12_P
  • MGT_TX12_N
  • J1-17
  • J1-19
  • J1-18
  • J1-20
  • MGTXRXP0_112
  • MGTXRXN0_112
  • MGTXTXP0_112
  • MGTXTXN0_112
1
  • MGT_RX13_P
  • MGT_RX13_N
  • MGT_TX13_P
  • MGT_TX13_N
  • J1-21
  • J1-23
  • J1-22
  • J1-24
  • MGTXRXP1_112
  • MGTXRXN1_112
  • MGTXTXP1_112
  • MGTXTXN1_112
2
  • MGT_RX14_P
  • MGT_RX14_N
  • MGT_TX14_P
  • MGT_TX14_N
  • J1-25
  • J1-27
  • J1-26
  • J1-28
  • MGTXRXP2_112
  • MGTXRXN2_112
  • MGTXTXP2_112
  • MGTXTXN2_112
3
  • MGT_RX15_P
  • MGT_RX15_N
  • MGT_TX15_P
  • MGT_TX15_N
  • J1-29
  • J1-31
  • J1-30
  • J1-32
  • MGTXRXP3_112
  • MGTXRXN3_112
  • MGTXTXP3_112
  • MGTXTXN3_112

Table 3: MGT lanes


There are 2 clock sources for the GTX transceivers. MGT_CLK1, MGT_CLK2, MGT_CLK4 and MGT_CLK7 are connected directly to B2B connector J3 and J1, so the clock can be provided by the carrier board. Clocks MGT_CLK0, MGT_CLK3, MGT_CLK5 and MGT_CLK6 are provided by the on-board clock generator (U2). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

BankTypeClock signalSourceFPGA PinNotes
109GTXMGT_CLK3_PU2, CLK3AMGTREFCLK1P_109, AF10Supplied by on-board Si5338A
MGT_CLK3_NU2, CLK3BMGTREFCLK1N_109, AF9
MGT_CLK2_PJ3-38MGTREFCLK0P_109, AD10Supplied by B2B connector J3
MGT_CLK2_NJ3-40MGTREFCLK0N_109, AD9
110GTXMGT_CLK0_PU2, CLK2AMGTREFCLK0P_110, AA8Supplied by on-board Si5338A
MGT_CLK0_NU2, CLK2BMGTREFCLK0N_110, AA7
MGT_CLK1_NJ3-39MGTREFCLK1P_110, AC8Supplied by B2B connector J3
MGT_CLK1_PJ3-37MGTREFCLK1N_110, AA7
111GTXMGT_CLK4_NJ1-40MGTREFCLK0P_111, U8Supplied by B2B connector J1
MGT_CLK4_PJ1-38MGTREFCLK0N_111, U7
MGT_CLK5_PU2, CLK1AMGTREFCLK1P_111, W8Supplied by on-board Si5338A
MGT_CLK5_NU2, CLK1BMGTREFCLK1N_111, W7
112GTXMGT_CLK6_PU2, CLK0AMGTREFCLK0P_112, N8Supplied by on-board Si5338A
MGT_CLK6_NU2, CLK0BMGTREFCLK0N_112, N7
MGT_CLK7_PJ1-37MGTREFCLK1P_112, R8Supplied by B2B connector J1
MGT_CLK7_NJ1-39MGTREFCLK1N_112, R7

Table 4: MGT reference clock sources

JTAG Interface

JTAG access to the Xilinx Zynq-7000 is provided through B2B connector J3.

JTAG Signal

B2B Connector Pin

TMSJ3-142
TDIJ3-147
TDOJ3-148
TCKJ3-141

Table 5: Zynq JTAG interface signals


JTAG access to the LCMXO2-1200HC System Controller CPLD U14 is provided through B2B connector J3.


JTAG Signal

B2B Connector Pin

M_TMSJ3-82
M_TDIJ3-87
M_TDOJ3-88
M_TCKJ3-81

Table 6: System Controller CPLD JTAG interface signals

Pin J3-136 'JTAGENB' of B2B connector J3 is used to access the JTAG interface of the SC CPLD. Set high to program the System Controller CPLD via JTAG interaface.

System Controller CPLD I/O Pins

Special purpose pins are connected to System Controller CPLD (U32) and have following default configuration:

Pin NameDirectionFunctionDefault Configuration
EXT_IO1 ... EXT_IO40in / outuser GPIO on B2Bsee current CPLD firmware
BOOTMODEininsignal forwarded to MIO9 and currently used as UART RX line
CONFIGXinoutsignal forwarded to MIO8 and currently used as UART TX line
NRST_INinnRESET inputexternal Board Reset
M_TDOoutCPLD JTAG interface



-
M_TDIin
M_TCKin
M_TMSin
JTAGENBinenable JTAGpull high for programming SC CPLD firmware
ETH1_RESEToutreset GbE PHY U18see current SC CPLD firmware
OTG-RSToutreset USB2 PHYs
U4 and U8
see current SC CPLD firmware
DONEinZynq control signalPL configuration completed
PROG_BoutPL configuration reset signal
PS_PORoutPS power-on reset
BM2/MIO4out

Bootmode Pin: SD or QSPI

MIO14inuser MIO pins

currently used as UART interface
MIO15out
LED2outRed LED D1 status signalsee current CPLD firmware
CPLD_GPIO0 ... CPLD_GPIO3in / outCPLD_GPIO3 used for Boot Modesee current CPLD firmware
FPGA_CPLD1 ... FPGA_CPLD4in /outuser GPIO to FPGA bank 9see current SC CPLD firmware
EN_1VoutPower controlenable signal DCDC U13 '1V'
PG_ALLin

power good signal all voltages powered up properly

→ Green LED D2 lights up.

Table 7: System Controller CPLD special purpose pins.

See also TE0783 CPLD reference Wiki page.

Default PS MIO Mapping

MIOFunctionConnected to
0USB2 PHY Resetvoltage level translator U30 → USB2 PHY U4
1QSPI0SPI Flash-CS
2QSPI0SPI Flash-DQ0
3QSPI0SPI Flash-DQ1
4QSPI0SPI Flash-DQ2
5QSPI0SPI Flash-DQ3
6QSPI0SPI Flash-SCK
7GbE PHY Resetvoltage level translator U30 → GbE PHY U18
8not used
3.3V pull-up for bootmode pin strapping
9not connected-
10SCLI²C clock line
11SDA
I²C data line
12-availabe on B2B pin J-22
13-availabe on B2B pin J-26
14UART RXinput, muxed to B2B by the SC CPLD
15UART TXoutput, muxed to B2B by the SC CPLD
16..27ETH0Ethernet RGMII PHY
28..39USB0USB0 ULPI PHY
40...45SD IOavailable on B2B connector J2 with 3.3V VCCIO
46...51eMMCconnected to on board eMMC Flash memory U28
52ETH0 MDC-
53ETH0 MDIO-

Table 8: Zynq PS MIO mapping

Gigabit Ethernet

The TE0783 is equipped with one Marvell Alaska 88E1512 Gigabit Ethernet PHYs (U18). The transceiver PHY is connected to the Zynq PS Ethernet GEM0. The I/O Voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHYs is supplied from an on board 25MHz oscillator (U11).

GbE PHY connection:

PHY PINZynq PS / PLNotes
MDC/MDIOMIO52, MIO53-
LED0Bank 9, Pin AC18-
LED1Bank 9, Pin AC19-
Interrupt-not connected
CLK125-125 MHz clock output not connected
CONFIG-When pin connected to GND, PHY Address is strapped to 0x00 by default
RESETnMIO7ETH1_RESET33 (MIO7) → voltage level translator U30 → ETH1_RESET
RGMIIMIO16..MIO27-
MDI-on B2B J2 connector

Table 9: General overview of the Gigabit Ethernet1 PHY signals

USB Interface

The TE0783 is equipped with one USB PHY USB3320 from Microchip (U4). The ULPI interface of the USB PHY is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V.

The reference clock input of the PHY is supplied from an on board 52MHz oscillator (U7).


USB2 PHY connection:

PHY PinZynq PS / PLB2B Connector J2Notes
ULPIMIO28..39-Zynq USB0 MIO pins are connected to the PHY
REFCLK--52MHz from on board oscillator (U7)
REFSEL[0..2]--000 GND, select 52MHz reference Clock
RESETBMIO0-OTG-RESET33 → voltage level translator U30 → OTG-RESET
CLKOUTMIO36-Connected to 1.8V selects reference clock operation mode
DP,DM-USB1_D_P, USB1_D_NUSB Data lines
CPEN-VBUS1_V_ENExternal USB power switch active high enable signal
VBUS-USB1_VBUSConnect to USB VBUS via a series resistor. Check reference schematic.
ID-OTG1_IDFor an A-Device connect to ground, for a B-Device left floating

Table 10: General overview of the Gigabit Ethernet2 PHY signals

I2C Interface

The on-board I2C components are connected to PS MIO bank 500 pins MIO10 ('MIO10_SCL') and MIO11 ('MIO11_SDA').

I2C addresses for on-board components:

DeviceICDesignatorI2C-AddressNotes
EEPROM24LC128-I/STU260x53user data
EEPROM24AA025E48T-I/OTU220x50MAC address EEPROM
RTCISL12020MIRZU170x6FTemperature compensated real time clock
Battery backed RAMISL12020MIRZU170x57Integrated in RTC
PLLSI5338A-B-GMRU20x70-

Table 11: Address table of the I2C bus slave devices

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U32) is provided by Lattice Semiconductor LCMXO2-4000HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.

See also TE0783 CPLD reference Wiki page.

eMMC Flash Memory

eMMC Flash memory device (U28) is connected to the Zynq PS MIO bank 501 pins MIO46..MIO51. eMMC chips MTFC4GMVEA-4M IT (Flash NAND-IC 2x 16 Gbit) is used with 4 GByte of memory density.

DDR3L Memory

By default TE0783-01 module has two 16bit wide IM (Intelligent Memory) IM4G16D3FABG-125I DDR3L SDRAM (DDR3-1600 Speedgrade) connected to the PS DDR memory bank 502, the chips are arranged into 32bit wide memory bus providing total of 1 GBytes of on-board RAM.

Another 4 chips are arranged into 64bit wide memory bus prodivding total of 2 GByte on-board RAM connected to the PL HP banks 34, 35 and 36.

Quad SPI Flash Memory

One quad SPI compatible serial bus Flash memory (U38) for FPGA configuration file storage is provided by Spansion S25FL256SAGBHI20 with 256 Mbit (32 MByte) memory density. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U18) is provided by Marvell Alaska 88E1512. The Ethernet PHY's RGMII interface is connected to the Zynq's PS MIO bank 501. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U11).

High-speed USB2 ULPI PHY

Hi-speed USB ULPI PHY (U4) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 bank 501 (see also section USB interface). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U7).

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U22) contain globally unique 48-bit node address, which are compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8 Kbit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. The MAC address EEPROM is accessible over I2C bus (see also section I²C interface).

Configuration EEPROM

The TE0783 board contains one EEPROM (U26) for configuration and general user purposes. The EEPROMs is provided by Microchip 24LC128-I/ST with 128 KBit memory density, the EEPROM is areaccessible over I2C bus (see also section I²C interface).

Programmable Clock Generator

There is a Silicon Labs I2C programmable clock generator Si5338A (U2) chip on-board. It's output frequencies can be programmed using the I2C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.

A 25.000000 MHz oscillator (U3) is connected to the pin IN3 and is used to generate the output clocks. The output voltage of the oscillator is provided by the 1.8V power rail, thus making output frequency available as soon as 1.8V is present. All 4 of the Si5338 clock outputs are connected to the MGT banks of the Zynq device. It is possible to use the clocks connected to the GTR bank in the user's logic design. This is achieved by instantiating a IBUFDSGTE buffer in the design.

Once running, the frequency and other parameters can be changed by programming the device using the I2C bus connected between the FPGA (master) and clock generator (slave). For this, proper I2C bus logic has to be implemented in FPGA.

SignalFrequencyNotes
IN1/IN2user

External clock signal supply from B2B connector J3, pins J3-38 / J3-40

IN3

25.000000 MHz

Fixed input clock signal from reference clock generator SiT8008BI-73-18S-25.000000E (U3)

IN4-LSB of the default I2C address, wired to ground mean address is 0x70

IN5

-

Not connected

IN6

-

Wired to ground
CLK0 A/B

-

reference clock 0 of Bank 112 GTX

CLK1 A/B

-

reference clock 1 of Bank 111 GTX

CLK2 A/B

-

reference clock 0 of Bank 110 GTX

CLK3 A/B-reference clock 1 of Bank 109 GTX

Table 12: General overview of the on-board quad clock generator I/O signals

Oscillators

The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Clock SourceSchematic NameFrequencyClock Destination
SiTime SiT8008AI oscillator, U61PS_CLK33.333333 MHzZynq SoC U1, pin A22
SiTime SiT8008AI oscillator, U33PL_CLK33.333333 MHzZynq SoC U1, pin AA18
Microchip DSC1123 oscillator, U15MIG_SYS_CLK_P / MIG_SYS_CLK_N200.0000 MHzZynq SoC U1, pins H9, G9
SiTime SiT8008BI oscillator, U3-25.000000 MHzQuad PLL clock generator U2, pin 3
Microchip DSC1123 oscillator, U31B9_CLK_P, B9_CLK_N125.0000 MHzZynq SoC U1, pins AD18, AD19
SiTime SiT8008AI oscillator, U7-52.000000 MHzUSB2 PHYs U4 and U8, pin 26
SiTime SiT8008BI oscillator, U11-25.000000 MHzGbE PHYs U18 and U20, pin 34

Table 13: Reference clock signals

On-board LEDs

LEDColorConnected toDescription and Notes
D1RedSystem Controller CPLD U32, bank 0Indicates power-up sequence completed.
D2GreenSystem Controller CPLD U32, bank 2Exact function is defined by SC CPLD firmware.

Table 14: On-board LEDs

Power and Power-on Sequence

Power Supply

Power supply with minimum current capability of 4A for system startup is recommended.

Power Consumption

Power InputTypical Current
VINTBD*
C3.3VTBD*

Table 15: Power consumption


 * TBD - To Be Determined soon with reference design setup.

To avoid any damage to the module, check for stabilized on-board voltages should be carried out (i.e. power good and enable signals) before powering up any Zynq's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

Power Distribution Dependencies

The Trenz TE0783 SoM is equipped with two quad DC-DC voltage regulators to generate required on-board voltage levels 1V, 3.3V, 1.8V, 1.2V_MGT, 1V_MGT. Additional voltage regulators are used to generate voltages 3.3V_SB, 1.5V, VTT, VTTREF for PS and PL memory bank, 1.8V_MGT and VCCAUX_IO.

There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

Figure 3: TE0783-01 Power Distribution Diagram


See also Xilinx datasheet DS191 for additional information. User should also check related base board documentation when intending base board design for TE0783 module.

Power-On Sequence

Power-on sequence is handled by the System Controller CPLD using "Power good"-signals from the voltage regulators:

Figure 4: TE0783-01 Power-on Sequence Diagram

Voltage Monitor Circuit

The voltages '1V' and '3.3V' are monitored by the voltage monitor circuit U27, which generates the PS_POR reset signal if monitored voltages have transient interruptions:

Figure 5: TE0783-01 Voltage Monitor Circuit

Power Rails

Power Rail Name on B2B ConnectorJ1 PinsJ2 PinsJ3 PinsDirectionNotes
VIN-165, 166, 167, 168-Inputexternal power supply voltage
C3.3V-147, 148-InputNormally leave unconnected
3.3V-

111, 112, 123, 124, 135 136

169, 170, 171, 172

-Outputinternal 3.3V voltage level
1.8V169, 170, 171, 172--Outputinternal 1.8V voltage level
EXT_IO_VCC99, 100--InputSC CPLD bank 1, 2 and 4 voltage
VCCIO_10--99, 100Inputhigh range I/O bank voltage
VCCIO_11--159, 160Inputhigh range I/O bank voltage
VCCIO_12-159, 160-Inputhigh range I/O bank voltage
VCCIO_13-99, 100-Inputhigh range I/O bank voltage
VBAT_IN--124Inputbackup battery voltage

Table 16: Module power rails

Bank Voltages

BankSchematic NameVoltageRangeNotes
0-3.3 V-FPGA configuration
502-1.5 V-DDR3-RAM port
109 / 110 / 111 / 112-1.2 V-MGT
500-3.3 V-PS MIO banks
501-1.8V-PS MIO banks
9 (HR)-3.3 V--
10 (HR)VCCIO_10user1.2V to 3.3V-
11 (HR)VCCIO_11user1.2V to 3.3V-
12 (HR)VCCIO_12user1.2V to 3.3V-
13 (HR)VCCIO_13user1.2V to 3.3V-
33 (HP)1.5V_PL1.5 V-64bit DDR3L SD-RAM
34 (HP)1.5V_PL1.5 V-
35 (HP)1.5V_PL1.5 V-

Table 17: Module I/O bank voltages

See Xilinx Zynq-7000 datasheet DS191 for the voltage ranges allowed.

Board to Board Connectors

The TE0783 SoM has three 160-pin double-row ASP-122952-01  Samtec connectors on the bottom side which mate with ASP-122953-01 Samtec connectors on the baseboard. Mating height is 5 mm.

Variants Currently In Production

Trenz shop TE0783 overview page
English pageGerman page

Technical Specifications

Absolute Maximum Ratings

Parameter

MinMax

Units

Notes

VIN supply voltage

-0.3

15

V

LTM4644 datasheet
VBAT supply voltage-0.36VTPS780180 datasheet
PS I/O supply voltage, VCCO_PSIO-0.53.6VXilinx document DS191
PS I/O input voltage-0.4VCCO_PSIO + 0.55VXilinx document DS191
HP I/O bank supply voltage, VCCO-0.52.0VXilinx document DS191
HP I/O bank input voltage-0.55VCCO + 0.55VXilinx document DS191
HR I/O bank supply voltage, VCCO-0.53.6VXilinx document DS191
HR I/O bank input voltage-0.55VCCO + 0.55VXilinx document DS191
Differential input voltage-0.42.625VXilinx document DS191
MGT reference clocks absolute input voltage-0.51.32VXilinx document DS191
MGT absolute input voltage-0.51.26VXilinx document DS191

Voltage on SC CPLD pins

-0.5

3.75

V

Lattice Semiconductor MachXO2 datasheet

Storage temperature

-40

+85

°C

See eMMC MTFC4GACAJCN datasheet

Table 18: Module absolute maximum ratings

Recommended Operating Conditions

ParameterMinMaxUnitsNotes
VIN supply voltage11.412.6V12V nominal power supply voltage
VBAT supply voltage2.25.5VTPS780180 datasheet
PS I/O supply voltage, VCCO_PSIO1.7103.465VXilinx document DS191
PS I/O input voltage–0.20VCCO_PSIO + 0.20VXilinx document DS191
HP I/O banks supply voltage, VCCO1.141.89VXilinx document DS191
HP I/O banks input voltage-0.20VCCO + 0.20VXilinx document DS191
HR I/O banks supply voltage, VCCO1.143.465VXilinx document DS191
HR I/O banks input voltage-0.20VCCO + 0.20VXilinx document DS191
Differential input voltage-0.22.625VXilinx document DS191
Voltage on SC CPLD pins-0.33.6VLattice Semiconductor MachXO2 datasheet
Operating Temperature Range-4085°CXilinx document DS191, industrial grade Zynq temperarure range

Table 19: Recommended operating conditions


Module operating temperature range depends also on customer design and cooling solution. Please contact us for options.

See Xilinx datasheet DS191 for more information about absolute maximum and recommended operating ratings for the Zynq-7000 chips.

Physical Dimensions

  • Module size: 85 mm × 85 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 5 mm

  • PCB thickness: 1.7 mm

All dimensions are shown in millimeters.

Figure 6: Module physical dimensions drawing

Revision History

Hardware Revision History

DateRevision

Notes

PCN LinkDocumentation Link
-01first production release-TE0783-01

Table 20: Hardware revision history table


Figure 7: Module hardware revision number

Document Change History


Date

Revision

Contributors

Description

  • Initial version

Table 21: Document change history

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