Table of contents
Set B2B Pin J3-136(JTAGENB) to VDD (3.3V).
- Set DIP S1-1 to OFF
- Use XMOD on J8 Pinheader
Available CPLD Firmware
- TE0784/<PCB Revision>/Firmware/
- Use files from the subfolders of your PCB revision
CPLD Firmware Update - General Requirements
- Lattice Diamond or Lattice Diamond Programmer is available for free on http://www.latticesemi.com/
- Lattice compatible JTAG Programmer, for example:
- Trenz TE0790 or Carrier with FTDI for JTAG
- Most JTAG programmer, which used FTDI Chip to translate USB to JTAG
- Digilent FTDI based programmer are not compatible with Lattice.
- JTAG must be connected to CPLD JTAG
- JTAG Enable Pin of CPLD must be selectable and set to VDD
- Correct CPLD Firmware (JED-File) from Trenz Electronic Download
CPLD Firmware Update - General Procedure
- Connect only one JTAG device to host PC.
- Close all other JTAG programs, like Xilinx tools (on WinOS check hw_server.exe is terminated).
- Enable CPLD JTAG access (See JTAG section on CPLD Firmware description)
- Connect JTAG
- Power on System
- Open Lattice Diamond Programmer
- Detect Cable and click "Ok"
For some devices second Port must be selected:
- Select Device (See CPLD Firmware overview description).
In the most cases select the correct detected device one time (it's yellow at first on the menue)
- Select correct Firmware from Download Area (JED File)
- Program CPLD:
- Disable CPLD JTAG access (See JTAG section on CPLD Firmware description)
- Restart System
More Information are available on the CPLD Firmware description and on the readme.txt included into the download zip.