Table of contents
CPLD Device with designator U1: LCMX02-256HC. This is the same as the standard configuration except that UART RXD and TXD pins are swapped.
- JTAG routing
- Pinheader routing
Firmware Revision and supported PCB Revision
See Document Change History
|Name / opt. VHD Name||Direction||Pin||Description|
|A||out||8||XMOD Pin Header / UART TXD (output from adapter)|
|ACBUS4||27||FTDI / currently_not_used|
|ACBUS5||28||FTDI / currently_not_used|
|ADBUS4||5||FTDI / currently_not_used|
|B||in||12||XMOD Pin Header / UART RXD (input to adapter)|
|BDBUS2||in||21||FTDI / currently_not_used|
|BDBUS3||out||20||FTDI / currently_not_used|
|C||out||9||XMOD Pin Header / TCK|
|D||in||11||XMOD Pin Header / TDO|
|E||in||14||XMOD Pin Header / LED|
|F||out||13||XMOD Pin Header / TDI|
|FT_B_RX / BDBUS1||out||25||FTDI|
|FT_B_TX / BDBUS0||in||23||FTDI|
|G||in||17||XMOD Pin Header / Pushbutton S1|
|H||out||16||XMOD Pin Header / TMS|
|JTAGEN||in||26||Enable JTAG access to CPLD for Firmware update (zero: normal IOs, one: CPLD JTAG access). Selectable over S2-1|
|TCK / ADBUS0||in||30||FTDI|
|TDI / ADBUS1||in||32||FTDI|
|TDO / ADBUS2||out||1||FTDI|
|TMS / ADBUS3||in||29||FTDI|
|ULED||out||10||LED D4 (RED)|
|XCLK||in||4||12 MHz OSCI Ref CLK / currently_not_used|
JTAG signals routed directly through the CPLD to 12 pin pinheader. Access between CPLD and pinheader can be multiplexed via JTAGEN (logical one for CPLD, logical zero for pinheader).
UART is routed through the CPLD.
ULED D4 (RED) is E xor not G
Appx. A: Change History and Legal Notices
- REV01 to older REV01
- no logical changes
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
|Date||Document Revision||CPLD Firmware Revision||Supported PCB Revision||Authors||Description|
|REV01||REV03,REV02||No changes, also PCB REV03 compatible|
|2017-04-26||v.5||REV01||REV02||John Hartfiel||REV01 finished (rework without logical changes released 2017-04-04)|
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