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Table of Contents

Overview

The Trenz Electronic TE0790 is an universal USB2.0 to JTAG, UART and GPIO adapter based on the FTDI FT2232H USB2 IC. The adapter board converts signals from USB2.0 to standard serial or parallel interfaces of Embedded Systems like JTAG, SPI, I²C and UART.
The board is equipped with a programmable System Controller CPLD provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family) to control the signals of the configured interfaces. The data stream of the USB2.0 port can be also converted to 8 independent GPIO's or used as FIFO.

In order to work with Xilinx tools special order must be used, in that case the EEPROM is pre-programmed and serialized and will be recognized by all Xilinx tools (ISE/Impact/Chipscope, Vivado Programmer/SDK..).

Following table describes the possible operation modes of the TE0790 adapter board. The operation modes are determined by the configuration of the FT2232H (done by programing the Configuration EEPROM) and the firmware implementation of the System Controller CPLD:

#FTDI
Channel A
FTDI
Channel B
Pins A to GNotes
1JTAG/SPI (MPSSE)UARTJTAG, UARTJTAG compatible to Xilinx, Lattice and open-source software that uses FTDI MPPSE
2JTAG/SPI (MPSSE)JTAG/SPI (MPSSE)JTAG, JTAGDual JTAG, only Channel A is Xilinx compatible
3UARTUARTUART, UARTDual UART
4I2CUARTI2C, UART 
5MPSSE 8x GPIO 
6 UART8x GPIO 
7UARTUARTnot usedUART to UART loopback
8not usedFast Serial FTDI 4-wire fast serial adapter, custom EEPROM is needed to enable this mode
9CPLD update onlynot useduser definedStandalone Module with CPLD and 8 user programmable I/O

Table 1: Initial delivery state of programmable devices on the module.

MPSSE - FTDI protocol that is used by JTAG and SPI adapters based on FTDI devices.

Important notice on TE0790-xx variants:

Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

Key Features

  • Xmod form-factor
    • size: 20 x 25 mm
    • M3 mounting hole
  • FT2232H
    • USB2.0 port High Speed (480 Mbps) and Full Speed (12 Mbps) compatible
    • Entire USB protocol handled on the chip
    • USB2.0 to JTAG, SPI and I²C conversion provided by the IC's Multi-Protocol Synchronous Serial Engine (MPSSE)
    • USB2.0 to UART conversion
    • Channel B UART RX/TX LED's
    • Mini-USB B connector (more rigid then micro-USB)
    • 93C56 EEPROM
  • Lattice XO2-256 CPLD
    • on board programmable using Lattice tools
    • 8 universal I/O pins
    • VCCIO either 3.3V or user supplied (1.8 to 3.3V)
    • RED user LED
    • 12 MHz clock from on-board Oscillator
  • Variable power supply of the XMOD adapter board
    • by Mini USB2.0 connector
    • by base-board through pin header J2
  • GREEN Power-on LED
  • User button
  • 4 position DIP switch
    • Choose CPLD program mode
    • FTDI EEPROM disable (not implemented in PCB REV 1)
    • Use VIO same as VCC
    • Use VCC from USB

Block Diagram

Figure 1: TE0790-02 block diagram.

Main Components

       

Figure 2: TE0790-02 main components.

  1. FTDI FT2232H IC U4
  2. 2x6 Pin Header (2.54mm, female), J2
  3. Mini USB B Connector J4
  4. Microchip 93AA56BT-I/OT Configuration EEPROM, U10
  5. DIP-switch S2
  6. Push button S1
  7. Lattice Semiconductor LCMXO2-256HC System Controller CPLD, U1
  8. SiTime SiT8008AI-73 oscillator @12MHz, U6
  9. Green LED, D1 (Power)
  10. Red LED, D4 (User)
  11. Red LED, D3 (UART RX)
  12. Red LED, D2 (UART TX)

Initial Delivery State

Storage device name

Content

Notes

Configuration EEPROM U10variant dependingonly programmed on TE-0790-xx,
not programmed on TE0790-xxL

Table 2: Initial delivery state of programmable devices on the module.

Signals, Interfaces and Pins

2x6 Pin Header

The 2x6 pin header (2.54mm grid size, female) J2 have to be connected to the corresponding pin header on the target system. The signal assignment of the pin header on the adapter board depends on the configuration of the System Controller CPLD firmware.

Basic pin assignment:

Signal J2 Pin NameJ2 Pin Name Signal
GND 1*GND
User DefinedCAUser Defined
VIO  VDD 3.3V
User DefinedDBUser Defined
User DefinedFEUser Defined
User DefinedHGUser Defined / Button (Reset_n)

Table 3: Pin header J2 signal assignment. *pin 1 on header J2


Top View

Bottom View flipped


Figure 3: J2 pin header signal assignment

The signals of the FTDI FT2232H chip are not directly connected to the pin header J2 but routed to the System Controller CPLD of the adapter board, which controls and by-passes the signals to the pin header J2.

Therefore, different signal assignments are made on the pin header J2 depending on the SC CPLD firmware:


Signal assignment on TE0790 CPLD - XMOD Standard:

FTDISignalPull up/down J2 Pin NameJ2 Pin Name Pull up/downSignalFTDI
 GND- 1*-GND 
ADBUS0TCK (output from adapter) CAupUART RXD (input to adapter)BDBUS1
 VIO-  -VDD 3.3V 
ADBUS2TDO (input to adapter)upDB UART TXD (output from adapter)BDBUS0
ADBUS1TDI (output from adapter) FEdownLED 
ADBUS3TMS (output from adapter) HGupButton (Reset_n) 

Table 4: Pin header J2 signal assignment with standard configuration firmware. *pin 1 on header J2


Signal assignment on Standard with RXD-TXD Swapped:

This is the same as the standard configuration except that UART RXD and TXD pins are swapped.

FTDISignalPull up/down J2 Pin NameJ2 Pin Name Pull up/downSignalFTDI
 GND- 1*-GND 
ADBUS0TCK (output from adapter) CA
UART TXD (output from adapter)BDBUS0
 VIO-  -VDD 3.3V 
ADBUS2TDO (input to adapter)upDB upUART RXD (input to adapter)BDBUS1
ADBUS1TDI (output from adapter) FEdownLED 
ADBUS3TMS (output from adapter) HGupButton (Reset_n) 

Table 5: Pin header J2 signal assignment with standard, but RXD-TXD swapped configuration firmware. *pin 1 on header J2


Signal assignment on TE0790 CPLD - XMOD DIP40:

On DIPFORTy, VIO Pin is connected with VDD 3.3V Pin.  UART RXD is connected to FPGA-Pin L13 and UART TXD to K15. Connect XMOD on the top-side (FPGA side) of the PCB.

FTDISignalPull up/down J2 Pin Name J2 Pin NamePull up/downSignalFTDI
 GND- 1*-GND 
BDBUS1UART RXD (input to adapter)upCA TCK (output from adapter)ADBUS0
 VIO-  -VDD 3.3 V 
BDBUS0UART TXD (output from adapter) DB TMS (output from adapter)ADBUS3
ADBUS1TDI (output from adapter) FEupTDO (input to adapter)ADBUS2
 not used HG CPLD User LED 'ULED' 

Table 6: Pin header J2 signal assignment with DIPFORTy firmware.

USB Interface

The USB2.0 interface is provided by the FTDI  FT2232H chip accessible by the Mini-USB B connector J4. The entire USB protocol is handled on chip and compatible to USB2.0 High Speed (480 MBps) and Full Speed (12 MBps).

On-board Peripherals

FTDI FT2232H IC

The FTDI FT2232H chip provides a variety of industry standard serial or parallel interfaces. On the TE0790 adapter board at current available SC CPLD firmware the functions USB2.0 to JTAG, UART and user GPIO's.

By programing the firmware of the SC CPLD and special EEPROM configurations further further functionalities are available of the FTDI chip which converts signals from USB2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H IC.

Configuration EEPROM

The external EEPROM can be used to customize the TE0790 adapter board by setting numerous parameters of the FT2232H IC, enabling different functionalities and configuring serial or parallel interfaces.

The EEPROM is programmable in-circuit over USB using a utility program called FT_PROG available from FTDI’s web site (www.ftdichip.com).

Important notice on TE0790-xx variants:

Do not access the FT2232H EEPROM using FTDI programming tools, doing so will erase normally invisible user EEPROM content and invalidate stored Xilinx JTAG license. Without this license the on-board JTAG will not be accessible any more with any Xilinx tools. Software tools from FTDI website do not warn or ask for confirmation before erasing user EEPROM content.

System Controller CPLD

The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces.

Signals of the serial or parallel interfaces are by-passed, forwarded and controlled by the System Controller CPLD.

The internal routing of the signals on the System Controller CPLD between the USB2.0 interface and pin header J2 depends on its configured firmware. CPLD can be set into JTAG chain via  S2-1 DIP Switch. Refer to the TE0790 CPLD Firmware for more information about the currently available System Controller CPLD firmware and for download.

DIP-switch

The DIP-switch S2 is to set different modes of powering the on-board components, the I/O voltages and to enable programming the adapter board CPLD by JTAG interface:

S2ONOFFDefaultDescription
1Normal modeAdapter board CPLD update modeONUpdate Mode JTAG access to SC CPLD only
2Do not use (illegal setting)Normal modeOFFMust be in OFF state always.
3VIO connected to 3.3VPower VIO from pin header J2OFFUser I/O Voltage
4Power 3.3V from USBPower 3.3V from pin header J2OFFPower on-board peripherals (FTDI chip & SC CPLD, ...)

Table 7: DIP-switch S2 setting description.

The voltages 3.3V (VCC) and VIO (variable SC CPLD I/O-voltage) can be configured by the DIP-switches S2-3 and S2-4:

S2-3S2-43.3V (VCC) Pin 5VIO Pin 6Description
OFFOFF3.3V from base (input**)VIO from base (input**)3.3V (pin 5) and VIO (pin 6) sourced from base
OFFON3.3V from USB* (output**)VIO from base (input**)VIO sourced from base by Pin 6
ONOFF3.3V from base (input**)3.3V from base (input**)VIO and 3.3V source by base (Pin 5 and Pin 6 are shorted and both must be sourced by 3.3V)
ONON3.3V from USB* (output**)3.3V from USB* (output**)

3.3V (pin 5) and VIO (pin 6) sourced USB (Pin 5 and Pin 6 are shorted and both are 3.3V)

  • *max. 100mA for external components (It's not recommended to supply FPGA Module)
      Attention: Do not use this setting, if base power supply is connected to this pins!  For more details see Power supply of the adapter board  section.
  • **view of XMOD

Table 8: DIP-switch S2 power setting description.

User Push Button

The user push button S1 directly connected to the SC CPLD manipulates pin G of the pin header J2 by driving it to GND.

On-board LEDs

The on-board LEDs indicates system status data transmission activities:

LED ColorConnected toDescription and Notes
D1Green3.3V3.3V power status LED
D2RedFTDI IC, 'RXLED'UART receive data activity
D3RedFTDI IC, 'TXLED'UART transmit data activity
D4RedSC CPLD, 'ULED'user LED, on standard SC CPLD firmware assigned to pins E and G, in DIPFORTy to G

Table 9: On-board LEDs.

Power and Power-On Sequence

Power supply of the adapter board

The XMOD can be powered via USB or with 3.3V on J2 pins, depending on DIP-switch settings. Max. ~100mA for external components are available on J2 3.3V Pin, if the power supply via USB is used.

Following diagram shows how the settings of the DIP-switches S2-3 and S2-4 determines the configuration of the on-board voltages:

Figure 4: TE0790 on-board voltages configuration

Power Rails

Power Rail Name

Pin Header J2

Mini USB B J4

Direction

Notes
3.3Vpin 5-both possibleon-board peripherals' VCC and core voltages
VIOpin 6-both possiblePin header J2 interface signals and SC CPLD VCCIO
VBUS-pin 1inputUSB bus power, nominal voltage 5 V ± 5%

 Table 10: power rails.

Variants Currently In Production

 Module Variant

Xilinx Vivado/SDK Support

Xilinx devices with 3rd Party ToolsAny other MPSSE based JTAG Tools
TE0790-02YesYesYes
TE0790-02LNoYesYes

Table 11: Module variants.

Variants with TE-0790-xxL do not include the ID String in EEPROM for direct support from Xilinx Vivado.

Technical Specifications

Absolute Maximum Ratings

ParameterMinMaxUnitsReference Document

3.3V

-0.34VFTDI FT2232H data sheet
VIO-0.53.75VLattice MachX02 Family data sheet
VBUS4.755.25VUSB2.0 Specification
Voltage on pins A - H-0.53.75VLattice MachX02 Family data sheet
Storage temperature-40100°CLED SML-P11 data sheet

Table 12: Module absolute maximum ratings.

Recommended Operating Conditions

ParameterMinMaxUnitsReference Document

3.3V

 2.3753.6VLattice MachX02 Family data sheet
VIO1.143.6VLattice MachX02 Family data sheet
VBUS4.755.25VUSB2.0 Specification
Voltage on pins A - H1.143.6VLattice MachX02 Family data sheet
Operating temperature-4085°CFTDI FT2232H data sheet

Table 13: Module recommended operating conditions.

Operating Temperature Range

Industrial grade: -40°C to +85°C.

The TE0790 USB2.0 adapter board is capable to be operated at industrial grade temperature range.

Physical Dimensions

  • Module size: 24,65mm × 20,02mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard pin headers: 9.5 mm.

  • PCB thickness: 1.6 mm.

  • Highest part on PCB: approx. 7 mm. Please download the step model for exact numbers.

All dimensions are given in millimeters and mil.

  

Figure 5: Module physical dimensions drawing.

Revision History

Hardware Revision History

DateRevision

Notes

PCNDocumentation Link
-

01

prototypes--
-02current available revision-TE0790-02

Table 14: Module hardware revision history.


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.


Figure 6: Module hardware revision number.

Document Change History

Date

Revision

Contributors

Description

John Hartfiel
  • DIP-Switch description
2017-11-16v.34Ali NaseriUpdated Power supply, DIP-Switch and CPLD section

2017-10-26

v.27
John Hartfiel
  • Update 2x6 Pin Header Figure 3
  • Update Links
2017-10-19
v.26
Ali Naseri
  • Initial document

Table 15: Document change history.

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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

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