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Overview

Lattice MachXO2-4000HC is a CPLD chip, that is used in TEB0912 board as a system management controller. The system controller implements power management same as power sequencing, . Rather than power management is the system controller responsible for reset generation, zynq initial configuration. System controller contains of some additional features same as debouncing the power button and displaying the power status with LEDs. The  JTAG and UART interfaces are routed  in the firmware of CPLD  from FTDI chip to FPGA.

Feature Summary

  • Power Management
  • Reset Management
  • JTAG Routing
  • Boot Mode
  • User IOs
  • LED and power state display
  • UART

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHDL NameDirectionPinPullup/DownBank PowerDescription
ALERT_NinB33UP+3.3V_STBDigital output . Interrupt or SMBus alert output of temperature sensors (TMP461AIRUNT- U43,U47,U52,U57,U4) and temperature sensor with integrated fan control (LM96163-U61) /currently_not_used 
CPLD_DEBUG0inoutA41UP+3.3V_STBCPLD debug pin 0
CPLD_DEBUG1inoutA2UP+3.3V_STBCPLD debug pin 1 /currently_not_used
CPLD_DEBUG2inoutB1UP+3.3V_STBCPLD debug pin 2 /currently_not_used
CPLD_DEBUG3inoutA3NONE+3.3V_STBCPLD debug pin 3 /currently_not_used
CPLD_HD0inoutB3UP+3.3V_STBHigh density IOs select 0 /currently_not_used
CPLD_HD1inoutB28UP+3.3V_STBHigh density IOs select 1 /currently_not_used
EN_VCCINToutB22DOWN+3.3V_STBEnable pin for +0.85V DC-DC converter (LTM4630EY-U42A)
EN_VTT_DDRoutA22DOWN+3.3V_STBEnable pin for 2A Peak Sink/Source DDR Termination Regulator (TPS51206-U2, U3)
EN+0.85V_GT_AVCC_PS/ EN_0V85_GT_AVCC_PSoutB21DOWN+3.3V_STBEnable pin for 1.5A low-dropout linear regulator (TPS74801DRC-U45)
EN+0.9V_GT_AVCC/ EN_0V9_GT_AVCCoutB14DOWN+3.3V_STBEnable pin for quad DC-DC microModule regulator with configurable 4A output array  for +0.9V output voltage (LTM4644EY-U44)
EN+1.0V/ EN_1V0outA46DOWN+3.3V_STBEnable pin for 1.5A low-dropout linear regulator with +1.0V output voltage (TPS74801DRC-U13)
EN+1.2V_DDR/ EN_1V2_DDRoutA34DOWN+3.3V_STBEnable pin for quad DC-DC microModule regulator with configurable 4A output array  for +1.2V output voltage (LTM4644EY-U53)
EN+1.2V_GT_AVTT/ EN_1V2_GT_AVTToutB16DOWN+3.3V_STBEnable pin for quad DC-DC microModule regulator with configurable 4A output array  for +1.2V output voltage (LTM4644EY-U48)
EN+1.2V_PLL_PS/ EN_1V2_PLL_PSoutA15DOWN+3.3V_STBEnable pin for 1.5A low-dropout linear regulator (TPS74801DRC-U46)

EN+1.3V_MGT_PS/
EN_1V3_GT_PS

outB15DOWN+3.3V_STBEnable pin for quad DC-DC microModule regulator with configurable 4A output array for +1.37V output voltage (LTM4644EY-U44) 
EN+1.8V/ EN_1V8outB13DOWN+3.3V_STBEnable pin for quad DC-DC microModule regulator with configurable 4A output array  for +1.8V output voltage (LTM4644EY-U53)
EN+1.8V_AUX/ EN_1V8_AUXoutA30DOWN+3.3V_STBEnable pin for 1.5A low-dropout linear regulator with +1.8V output voltage  (TPS74801DRC-U49,U50,U51)
EN+1.8V_GT_AVTT_PS/ EN_1V8_GT_AVTT_PSoutB20DOWN+3.3V_STBEnable pin for 1.5A low-dropout linear regulator with +1.8V output voltage  (TPS74801DRC-U54)
EN+2.5V_DDR/ EN_2V5_DDRoutA44DOWN+3.3V_STBEnable pin for 1.5A low-dropout linear regulator with +2.5V output voltage  (TPS74801DRC-U55, U56)
EN+2V_MGT_PS/ EN_2V0_GT_PSoutA21DOWN+3.3V_STBEnable pin for quad DC-DC microModule regulator with configurable 4A output array  for +2.0V output voltage (LTM4644EY-U48)
EN+3.3V/ EN_3V3outB18DOWN+3.3V_STBEnable pin for quad DC-DC microModule regulator with configurable 4A output array  for +3.3V output voltage (LTM4644EY-U1)
EN+5V_BIAS/ EN_5V_VBIASoutA17DOWN+3.3V_STBEnable pin for low dropout linear regulator with +5V output voltage (ADP7102ACPZ-U58)
EXT_STATUS_LED_GoutB9NONE+3.3V_STBExternal status LED green (J40-Pin2) /currently_not_used
EXT_STATUS_LED_RoutA25NONE+3.3V_STBExternal status LED red (J40-Pin3) /currently_not_used
FAN_ENoutB29UP+3.3V_STBEnables a smart high-side power switch to drive the FAN (BTS41411N-U60)
FPGA_DONEinA24UP+3.3V_STBFPGA PL configuration done indicator
FTDI_PWR_EN_NinA36UP+3.3V_STBActive low power enable output of FTDI chip (FT2232H56Q-U38)
FTDI_RXoutA35NONE+3.3V_STBUART RXD of FTDI chip (FT2232H56Q-U38)
FTDI_TCKinA45NONE+3.3V_STBFTDI JTAG clock pin (FT2232H56Q-U38)
FTDI_TDIinA47NONE+3.3V_STBFTDI JTAG data input pin (FT2232H56Q-U38)
FTDI_TDOoutA48NONE+3.3V_STBFTDI JTAG data output pin (FT2232H56Q-U38)
FTDI_TMSinB34NONE+3.3V_STBFTDI JTAG mode select pin (FT2232H56Q-U38)
FTDI_TXinB27NONE+3.3V_STBUART TXD of FTDI chip (FT2232H56Q-U38)
I2C_SCL_CPLDinoutB32UP+3.3V_STBI2C clock pin that connected to all temperature sensors and current sensor /currently_not_used
I2C_SDA_CPLDinoutA42UP+3.3V_STBI2C data pin that connected to all temperature sensors and current sensor /currently_not_used
JTAGENinB30DOWN+3.3V_STBJTAG enable input pin of CPLD (Dip switch S4-1) If logical low, JTAG routed to FPGA. If logical high, CPLD access. 
MIO30 / MIO30_UART0_RXDoutA8NONE+1.8VMIO30 pin of FPGA (XCZU11EG-1FFVC1760I- U30R)
MIO31 /MIO31_UART0_TXDinA9NONE+1.8VMIO31 pin of FPGA (XCZU11EG-1FFVC1760I- U30R)
MIO32 / MIO32_UART1_TXDinB8NONE+1.8V

MIO32 pin of FPGA (XCZU11EG-1FFVC1760I- U30R)
/currently_not_used

MIO33 / MIO33_UART1_RXDoutB7NONE+1.8V

MIO33 pin of FPGA (XCZU11EG-1FFVC1760I- U30R)
/currently_not_used

MRoutA26UP+3.3V_STBManual-reset that connected to MR pin of ultralow supply-current voltage monitor chip (TPS3106K33DBVR-U73)
NetU68_B2
B2

/currently_not_used
PG_VCCINTinB23UP+3.3V_STBPower good pin for +0.85V DC-DC converter (LTM4630EY-U42A)
PG+0.85V_GT_AVCC_PS/ PG_0V85_GT_AVCC_PS inB12UP+3.3V_STBPower good pin for 1.5A low-dropout linear regulator for +0.85V output voltage (TPS74801DRC-U45) 
PG+0.9V_GT_AVCC/ PG_0V9_GT_AVCCinA18UP+3.3V_STBPower good pin for quad DC-DC microModule regulator with configurable 4A output array  for +0.9V output voltage (LTM4644EY-U44)
PG+1.0V/ PG_1V0inB35UP+3.3V_STBPower good pin for 1.5A low-dropout linear regulator with +1.0V output voltage (TPS74801DRC-U13)
PG+1.2V_DDR/ PG_1V2_DDR inA33UP+3.3V_STBPower good pin for quad DC-DC microModule regulator with configurable 4A output array  for +1.2V output voltage (LTM4644EY-U53)
PG+1.2V_GT_AVTT/ PG_1V2_GT_AVTTinA11UP+3.3V_STBPower good pin for quad DC-DC microModule regulator with configurable 4A output array  for +1.2V output voltage (LTM4644EY-U48)
PG+1.2V_PLL_PS/ PG_1V2_PLL_PSinA28UP+3.3V_STBPower good pin for 1.5A low-dropout linear regulator for +1.2V output voltage (TPS74801DRC-U46)
PG+1.3V_MGT_PS/ PG_1V3_MGT_PSinA20UP+3.3V_STBPower good pin for quad DC-DC microModule regulator with configurable 4A output array  for +0.9V output voltage (LTM4644EY-U44)
PG+1.8V/ PG_1V8inB25UP+3.3V_STBPower good pin for quad DC-DC microModule regulator with configurable 4A output array  for +1.8V output voltage (LTM4644EY-U53)
PG+1.8V_AUX/ PG_1V8_AUXinA27UP+3.3V_STBPower good pin for 1.5A low-dropout linear regulator with +1.8V output voltage  (TPS74801DRC-U50)
PG+1.8V_AUX_PS/
PG_1V8_AUX_PS
inB10UP+3.3V_STBPower good pin for 1.5A low-dropout linear regulator with +1.8V output voltage  (TPS74801DRC-U51)
PG+1.8V_GT_AUX/ PG_1V8_GT_AUXinA13UP+3.3V_STBPower good pin for 1.5A low-dropout linear regulator with +1.8V output voltage  (TPS74801DRC-U49)
PG+1.8V_GT_AVTT_PS/ PG_1V8_GT_AVTT_PSinA16UP+3.3V_STBPower good pin for 1.5A low-dropout linear regulator with +1.8V output voltage  (TPS74801DRC-U54)
PG+2.5V_DDR/ PG_2V5_DDRinA32UP+3.3V_STBPower good pin for 1.5A low-dropout linear regulator with +2.5V output voltage  (TPS74801DRC-U55)
PG+2.5V_PL_DDR/ PG_2V5_PL_DDRinA38UP+3.3V_STBPower good pin for 1.5A low-dropout linear regulator with +2.5V output voltage  (TPS74801DRC-U56)
PG+2V_MGT_PS/ PG_2V_MGT_PSinA1UP+3.3V_STBPower good pin for quad DC-DC microModule regulator with configurable 4A output array  for +2.0V output voltage (LTM4644EY-U48)
PG+3.3V/ PG_3V3inA23UP+3.3V_STBPower good pin for quad DC-DC microModule regulator with configurable 4A output array  with +3.3V output voltage (LTM4644EY-U1)
PWR_BTNinA12UP+3.3V_STBPower button input (J40-Pin1)
PWR_STAT_GRNoutB24NONE+3.3V_STBRed LED for power status display ( D11-Red)
PWR_STAT_REDoutA31NONE+3.3V_STBGreen LED for power status display (D12-Green)
SRST_BinoutB5UP+1.8VPS software reset (Active Low) (XCZU11EG-1FFVC1769I- U30S)
TCKoutA5NONE+1.8VZynq JTAG clock pin (XCZU11EG-1FFVC1760I- U30S)
TDIoutB4NONE+1.8VZynq JTAG data input pin (XCZU11EG-1FFVC1760I- U30S)
TDOinA6NONE+1.8VZynq JTAG data output pin (XCZU11EG-1FFVC1760I- U30S)
THERM_NinA40UP+3.3V_STBOvertemperature termal shutdown pin of temperature sensors ( TMP461, U43,U47,U52,U57,U4) and temperature sensor with integrated fan control (LM96163-U61)  /currently_not_used
TMSoutA7NONE+1.8VZynq JTAG mode select pin (XCZU11EG-1FFVC1760I- U30S)


Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA is multiplexed via JTAGEN pin of CPLD (B30) (logical one for CPLD, logical zero for FPGA).

CPLD JTAGEN (Dip switch S4-1)Description
0FPGA access
1CPLD access

Boot Mode

TEB0912 supports JTAG, QSPI and SD card boot modes. Boot mode depends on the logic state of  S2 dip switch pins that are connected with FPGA boot mode configuration pins.

S2-4S2-3S2-2S2-1Boot Mode
OFFOFFOFFOFFPS JTAG
OFFOFFONOFFQuad-SPI (32b)
ONONONOFFSD1 LS (3.0)

Power

In this board the CPLD is responsible for controlling and monitoring of power supply of the board. There are various DC-DC converter or regulators. To control every converter chip or regualtor the CPLD monitors power good outputs of regulators or DC-DC converters continuously to avoid over-voltage in the power system.

Enable SignalPower Good SignalDomainSchematic PageInput power NetRegulator/ DC-DC ConverterOutput power Net
EN+1.0VPG+1.0V
PCIe_Switch_PWR+1.37VTPS74801DRC+1.0V
EN+2.5V_DDRPG+2.5V_DDR
PG+2.5V_PL_DDR

POWER3
POWER3
+3.3V
+3.3V
TPS74801DRC
TPS74801DRC
+2.5V_DDR
+2.5V_PL_DDR
EN+1.8VPG+1.8V
POWER3+12VLMT4644EY+1.8V
EN+1.2V_DDRPG+1.2V_DDR
POWER3+12VLMT4644EY+1.2V_DDR
EN+1.8V_AUX

PG+1.8V_AUX
PG+1.8V_GT_AUX
PG+1.8V_AUX_PS


POWER2
POWER2
POWER2
+2V_MGT_PS
+2V_MGT_PS
+2V_MGT_PS
TPS74801DRC
TPS74801DRC
TPS74801DRC
+1.8V_AUX
+1.8V_GT_AUX
+1.8V_AUX_PS
EN+1.2V_PLL_PSPG+1.2V_PLL_PS
POWER1+1.37VTPS74801DRC+1.2V_PLL_PS
EN+0.85V_GT_AVCC_PSPG+0.85V_GT_AVCC_PS
POWER1+1.37VTPS74801DRC+0.85V_GT_AVCC_PS
EN+1.8V_GT_AVTT_PSPG+1.8V_GT_AVTT_PS
POWER3+2V_MGT_PSTPS74801DRC+1.8V_GT_AVTT_PS
EN+1.2V_GT_AVTTPG+1.2V_GT_AVTT
POWER2+12VLTM4644EY+1.2V_GT_AVTT
EN+5V_BIAS--
POWER6+12VADP7102ACPZ-5.0-R7+5V_BIAS
EN+0.9V_GT_AVCC

PG+0.9V_GT_AVCC


POWER1+12VLTM4644EY+0.9V_GT_AVCC
EN+1.3V_MGT_PSPG+1.3V_MGT_PS
POWER1+12VLTM4644EY+1.37V
EN+2V_MGT_PSPG+2V_MGT_PS
POWER2+12VLTM4644EY+2V_MGT_PS
EN_VTT_DDR---
POWER4+3.3V
+3.3V
TPS51206DSQ
TPS51206DSQ
VTT_DDR_PL
VTT_DDR_PS
EN+3.3VPG+3.3V
POWER4+12VLTM4644EY+3.3V
EN_VCCINTPG_VCCINT
POWER0+12VLTM4630EY+0.85V_VCCINT

State Machine Diagram


LED

Green LED

StateBlink sequenceComment
IDLEOFFPower sequencing can not be started. Power button is not pushed or is not pushed correctly.
STAGE1ooooooo*Power good signal PG_VCCINT is faulty.
STAGE2oooooo**The following power good signals are faulty. The error may be due to a problem in a corresponding DC-DC converter or regulator.
PG_0V9_GT_AVCC
PG_1V3_MGT_PS
PG_0V85_GT_AVCC_PS
PG_1V2_PLL_PS
STAGE3ooooo***

The following power good signals are faulty. The error may be due to a problem in a corresponding DC-DC converter or regulator.
PG_2V_MGT_PS
PG_1V8_AUX
PG_1V8_AUX_PS
PG_1V8_GT_AUX
PG_1V8_GT_AVTT_PS

STAGE4oooo****Power good signal PG_1V2_GT_AVTT is faulty.
STAGE5ooo*****The following power good signals are faulty. The error may be due to a problem in a corresponding DC-DC converter or regulator.
PG_1V8
PG_3V3
PG_2V5_DDR
PG_2V5_PL_DDR
PG_1V2_DDR
PG_1V0
WAIT_RDY********The state machine remains in this stage as soon as a counter is not overflowed. After overflowing the counter the state machine  will jump in the next stage.
RDYONPower is ok and the FPGA is configured successfully.


RED LED

StatusBlink sequenceComment
pg_all = '0'********One of the power good signals are faulty. The error may be due to a problem in a DC-DC converter or regulator.
MR = '0'*****oooReset button is pushed.
SRST_B ='0'****ooooPS software reset (Active Low) is activated.
FPGA_DONE ='0'***oooooFPGA PL is not configured.
FPGA_DONE ='0'**ooooooFPGA PL is not configured.
FTDI_PWR_EN_N='1'*oooooooFTDI chip USB SUSPEND mode or device has not been configured.
elseOFF


Appx. A: Change History and Legal Notices

Revision Changes

  • Changes REV01 to REV02:
    • Power Management
    • FAN enable
    • LED blink sequencing
  • Changes REV00 to REV01:
    • Power on (min)
    • UART
    • JTAG

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

REV02REV02, REV03
  • REV02 release
  • Firmware release (SC-PGM-TEB0912-02_SC0912-02_20191127.zip

All


Legal Notices

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Technology Licenses

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REACH, RoHS and WEEE

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