TEBF0808 CPLD

S5-4

ON

1.8V

S5-4

OFF

1.2V

PCie

Power On Reset_N(pwr_rdy), MIO31

USB(PHY+HUB)

Power On Reset_N(pwr_rdy), MIO30

Modul PLL

Power On Reset_N(pwr_rdy)

PS_POR_B

Reset Button (hold long time ~3s), zynq_reset_ready

PS_SRST_B

Reset Button (hold short time ~1s), zynq_reset_ready

FMC_FAN_EN

Power On Reset_N(pwr_rdy)

I2C_RST

Power On Reset_N(pwr_rdy)

ETH_RST

Power On Reset_N(pwr_rdy), MIO24

ON

CPLD Access on both CPLD

OFF

FMC JTAG Access

JTAG_TCK

MIO26

JTAG_RTCK

JTAG_TCK

JTAG_TDI

MIO27

JTAG_TDO

MIO28

JTAG_TMS

MIO29

JTAG_SRST

not usedconnected only to FPGA RGPIO

JTAG_TRST

not used, connected only to FPGA RGPIO

ON

ON

Default, boot from SD/microSD or SPI Flash if no SD is detected

OFF

ON

Boot from eMMC

ON

OFF

Boot mode PJTAG0

OFF

OFF

Boot mode main JTAG

PERSTn

Power On reset and MIO31

SD_SEL

CD Pin form microSD selects the SD Card, microSD has higher priority

CD (MIO45)

mircoSD and SD Card detect

WP(MIO44)

0 when miroSD is used else SD card detect (forrward over Master CPLD)

XMOD_TXD

ZynqMP TX(MIO43), when PWR Ready else 1

XMOD_RXD

to ZynqMP RX(MIO42), when PWR Ready else 1

XMOD_TXD

Debug output, when XMOD Button is pressed else RX loopback

XMOD_RXD

Debug input(currently no function), when XMOD Button is pressed else TX loopback

CAN_TX

SC18(FPGA LOC depends on module)

CAN_RX

SC19(FPGA LOC depends on module)

CAN_S

SC16(FPGA LOC depends on module)

CAN_FAULT

Monitoring over RGPIO only

USB_RST

Power On Reset_N and MIO30 (over slave CPLD)

USBH_RST

Power On Reset_N and MIO30 (over slave CPLD)

USBH_MODE0

const 1

USBH_MODE1

const 1

DP_EN

Power On Reset_N

DP_RX

to SC10 when SC11 is 0 else Z

DP_TX

SX10

DP_DE

SC11

DP_HPD

SC12

SFP1_TX_DIS

const 0 (Enabled)

SFP2_TX_DIS

const 0 (Enabled)

I2C_RST

Power On Reset_N

ETH_RST

Power On Reset_N and MIO24 (over slave CPLD)

PHY_CONFIG

const 1

******** (slow blinking)

~0,7 Hz

continuous blinking, like SFP LEDs or Enclosure HD LED when board is powered down

******** (fast blinking)

~5,8 Hz

continuous blinking, like D6 LED or Enclosure Power LED when board is powered down

*****ooo

~0,7 Hz, duty cycle 5/8

5 times fast blink with a break

****oooo

~0,7 Hz, duty cycle 4/8

4 times fast blink with a break

***ooooo

~0,7 Hz, duty cycle 3/8

3 times fast blink with a break

**oooooo

~0,7 Hz, duty cycle 2/8

2 times fast blink with a break

*ooooooo

~0,7 Hz, duty cycle 1/8

1 times fast blink with a break

ON

---

LED ON

OFF

---

LED OFF

D7

Red

status

D6

Green

status

J10 Power LED

Blue (symbol light bulb)

status/user

J10 HD LED

Red (symbol drive)

status/user

XMOD1 D4

Red

status

XMOD2 D4

Red

status/user

SFP D1

Red

status/user

SFP D8

Green

status/user

D17 - USB HUB LED (Suspend)

Green

status

ON, no USB connected, OFF, USB connected

SFP D9

Red

status/user

SFP D10

Green

status/user

ETH J7

Yellow

status

ETH J7

Green/Orange

status

D4

Green

status/user

D5

Red

status/user

Reset Button (SW)

for monitoring only

PS POR

for monitoring only

PS ERR Stat

for monitoring only

PS ERR

for monitoring only

PS Init

for monitoring only

PCIe Reset

for monitoring only

USB Reset

for USB Reset and monitoring

Power On Reset

for Power On Reset and monitoring

inter FPGA

Data from Slave RGPIO to Master RGPIO (for test only)

FPGA Read (23)

JTAG_SRST

FPGA Read (22)

JTAG_TRST

FPGA Read (21)

FMC_CLKDIR

FPGA Read (20)

SD_WP

FPGA Read (19)

unused 0

FPGA Read (18)

SW4

FPGA Read (17)

SW3

FPGA Read (16)

XMOD_G

FPGA Read (15 dt 13)

PHY LEDs

FPGA Read (12)

CAN_FAULT

FPGA Read (11 dt 8)

current RGPIO Mux

FPGA Read (7 dt 0)

Data depends on MUX:

FPGA Write (23 dt 12)

unused

FPGA Write (11 dt 8)

RGPIO Mux, see FPGA Read (7 dt 0) , when RGIO active

FPGA Write (7 dt 6)

unused

FPGA Write (5 dt 0)

Diverse LED controll(see LED description) , when RGIO active

FPGA Read (23)

PLL_LOL

FPGA Read (22)

PG_PLL

FPGA Read (21)

PG_PL

FPGA Read (20)

PWROK and pwrok_force_zero_n

FPGA Read (19)

fmc_sanity_check

FPGA Read (18)

POK_FMC

FPGA Read (17)

PG_GT_R

FPGA Read (16)

PG_GT_L

FPGA Read (15)

PG_PSGT

FPGA Read (14)

PG_FPD

FPGA Read (13)

PG_DDR

FPGA Read (12)

PG_LPD

FPGA Read (11 dt 8)

current Boot Mode

FPGA Read (7)

ERR_STAT

FPGA Read (6)

ERROR

FPGA Read (5)

SD_CD_B

FPGA Read (4)

SD_CD_S

FPGA Read (3)

unused const 1

FPGA Read (2)

XMOD_BTN

FPGA Read (1)

SW2

FPGA Read (0)

SW1

FPGA Write (23 dt 8)

unused

FPGA Write (7dt 0)

Readable over Master CPLD-SoC RGPIO, when RGIO active

CPLD REV07 to REV08

• add major and minor revision number to uart string

• bugfix DP_EN  inverted

• reduce statistic cnt size to save resources for newer diamond version

• add X6 as optional ETH Reset from SOM(over MIO24 from Slave CPLD)

CPLD REV06 to REV07

• complete rework

• add inter CPLD RGPIO

• new LED debugging sequencing

• simple UART output with Revision Number and some statistic on second XMOD

CPLD REV05 to REV06

• BUGFIX: renamed SC19 to SC17

• Connect FMC JTAG to XMOD2 JTAG

• Connect PJTAG0 (MIO29..26) to JTAG Pin Header J30

• Connect CAN to PL

• RGPIO Pin changes

CPLD REV04 to REV05

• SD WP

• XMOD LED access over PL

Older Revision (PCB REV03) to CPLD REV04

• Fix USB HUB Mode default state over RGPIO

• Invert JLED2B over RGPIO

Older Revision (PCB REV02) to CPLD REV04

• Add all functionality from older Revision (PCB REV03)

CPLD REV07 to REV08

• PSON inverted

• Add MIO24 as additional ETH reset from SoM, and use X6 to forward it to Master CPLD

• remove unused aud_clk_c constrain

CPLD REV06 to REV07

• complete rework

• add variants (power up and SD)multi-functions for buttons

• power on and power downs sequencing

  • module complete disable on power down

  • power on sequencing

  • power down sequencing --> can be forced with power button (hold longer)

• Soft PS or PS POR Reset on Reset button (hold longer for PS POR Reset)

• add inter CPLD RGPIO

• new SoC RGPIO Pinout

• removed reboot for pcie initialization

• new LED debugging sequencing

• Disabled UART on power down state

• bugfix WP pin for microSD slot

• removed PCIe Reboot.

CPLD REV05 to REV06

• LED Status changes of LED D2 D3 and HD_LED, XMOD LED

• extended Power Management

CPLD REV04 to REV05

• PS reboot via FSBL over MIO30 (need for proper PCI initialization on first power on without press Reset Button)

• SD Boot from micoSD only if switch S5-1/-2 is selected to ON

• RGPIO connection

• Add SD WP to FPGA

• Power, Rest Button debounced

• direct LED access via MIO and PL

Older Revision (PCB REV03) to CPLD REV04

• Bugfix: PCIe Reset Pin location.

• Bugfix: Swapping HDLED and PWRLED location.

• Bugfix: MEMS_CLKIN Pin location.

• Add XMOD 1 LED

Older Revision (PCB REV02) to CPLD REV04

• Add all functionality from older Revision (PCB REV03)

REV08

REV05

• Document Style Update

• REV08

2024-10-30

2019-05-06

v.13

REV07

REV03,REV04*

• REV07 finished

• *please write to Trenz Electronic support for PCB REV02

2019-05-06

All