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Overview

Firmware for PCB-Master CPLD with designator U17. Use first CPLD Device in Chain: LCMX02-1200HC.

Firmware for PCB-Slave CPLD with designator U39.  Use second CPLD Device in Chain: LCMX02-1200HC.

There are 3 different Firmware variants available:

  1. (Default): SCM_0xA_default.jed/SCS_0xA_default.jed
  2. (optional): SCM_0xB_powerdown_disabled.jed/SCS_0xB_powerdown_disabled.jed - Power down Sequencing is disabled (See Note Power Management).
  3. (optional): SCM_0xC_msdboot_disabled.jed/SCS_0xC_msdboot_disabled.jed - CD Pin of MicroSD will not influence boot Mode (mircoSD can be used as Filesystem and system Boots from QSPI)

Feature Summary

  • Power Management (Slave CPLD)
  • Reset Management  (both)
  • CPLD JTAG (both)
  • FMC JTAG / PJTAG (Master CPLD)
  • FMC VADJ Power (Master CPLD)
  • Boot Mode (Slave CPLD)
  • PCIe (Slave CPLD)
  • SD  (both)
  • UART SoC (Slave CPLD)
  • UART (Debug) (Master CPLD)
  • CAN (Master CPLD)
  • USB (Master CPLD)
  • DisplayPort (Master CPLD)
  • SFP (Master CPLD)
  • I2C (Master CPLD)
  • LEDs (both)
  • RGPIO (both)


Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinBank PowerDescriptionCPLD
C_T1
243V3SB / currently_not_used U17
C_T2
263V3SB / currently_not_used U17
C_T3
253V3SB / currently_not_used U17
C_TCKin1313V3SBJTAG J28 (XMOD2) / FMC JTAG
U17
C_TDIin1363V3SBJTAG J28 (XMOD2) / FMC JTAG
U17
C_TDO1 / C_TDOout1373V3SBJTAG J28 (XMOD2) / FMC JTAG
U17
C_TMSin1303V3SBJTAG J28 (XMOD2) / FMC JTAG
U17
CAN_FAULT
1063V3SBCANU17
CAN_RXin1073V3SBCANU17
CAN_Sout1053V3SBCANU17
CAN_TXout1043V3SBCANU17
CLK_125MHz / PHY_CLKin701.8V / currently_not_used U17
CON_NTRST / JTAG_TRSTin1173V3SBJTAG, Connector J30U17
CON_RTCK / JTAG_RTCKout1253V3SBJTAG, Connector J30U17
CON_sRST / JTAG_SRSTin1273V3SBJTAG, Connector J30U17
CON_TCK / JTAG_TCKin1223V3SBJTAG, Connector J30U17
CON_TDI / JTAG_TDIin1193V3SBJTAG, Connector J30U17
CON_TDO / JTAG_TDOout1263V3SBJTAG, Connector J30U17
CON_TMS / JTAG_TMSin1213V3SBJTAG, Connector J30U17
DIR_T1
233V3SB / currently_not_used U17
DIR_T2
283V3SB / currently_not_used U17
DIR_T3
273V3SB / currently_not_used U17
DP_AUX_DE / DP_DEout923V3SBDisplay PortU17
DP_AUX_RX / DP_RXin913V3SBDisplay PortU17
DP_AUX_TX / DP_TXout933V3SBDisplay PortU17
DP_ENout773V3SBDisplay PortU17
DP_TX_HPD / DP_HPDin943V3SBDisplay PortU17
ETH_RSTout621.8VETH ResetU17
EX_IO1
1123V3SB / currently_not_used U17
EX_IO2
1133V3SB / currently_not_used U17
EX_IO3
1143V3SB / currently_not_used U17
EX_IO4
1153V3SB / currently_not_used U17
F2_EN
193V3SB / currently_not_used U17
F2PWM
203V3SB / currently_not_used U17
F2SENSE
213V3SB / currently_not_used U17
FMC_CLK_DIR / FMC_CLKDIRin733V3SBFMCU17
FMC_TCKout953V3SBFMCU17
FMC_TDIout963V3SBFMCU17
FMC_TDOin973V3SBFMCU17
FMC_TMSout983V3SBFMCU17
FMC_VID0out1393V3SBFMCU17
FMC_VID1out1403V3SBFMCU17
FMC_VID2out1413V3SBFMCU17
GND
843V3SBREV03 unconnected / currently_not_usedU17
HDIO_SC10 / SC10out601.8VFPGA / DP_RX or 'Z'U17
HDIO_SC11 / SC11in591.8VFPGA / DP_DEU17
HDIO_SC12 / SC12out581.8VFPGA / DP_HPDU17
HDIO_SC13 / SC13out571.8VFPGA / RGPIO TXU17
HDIO_SC14 / SC14in561.8VFPGA / RGPIO RXU17
HDIO_SC15 / SC15in551.8VFPGA / RGPIO CLKU17
HDIO_SC16 / SC16in541.8VFPGA / CAN_SU17
HDIO_SC17 / SC17in521.8VFPGA / XMOD LED U17
HDIO_SC18 / SC18in681.8VFPGA / CAN_TXU17
HDIO_SC19 / SC19out691.8VFPGA / CAN_RXU17
I2C_RSTout611.8VI2CU17
JTAGENB
1203V3SBexternal Pin for CPLD Firmware Update U17
LED_1A / JLED1out1093V3SBUSB3.0 LED JellowU17
LED_2A / JLED2Aout1113V3SBUSB3.0 LED Green/OrangeU17
LED_2B / JLED2Bout1103V3SBUSB3.0 LED Green/OrangeU17
MIO26out411.8VMIO / PJTAGU17
MIO27out401.8VMIO / PJTAGU17
MIO28in391.8VMIO / PJTAGU17
MIO29out381.8VMIO / PJTAGU17
OCLK_EN / OSC_ENout743V3SBProgrammable Oscillator U45U17
PHY_CONFIGout651.8VETH PHYU17
PHY_LED0in671.8VETH PHYU17
PHY_LED1in863V3SBETH PHYU17
PHY_LED2in853V3SBETH PHYU17
SC_CLK0 / CLK0in763V3SB/ currently_not_usedU17
SC_CLK1 / CLK1in753V3SB/ currently_not_usedU17
SC_IO0 / X0out501.8VMTS dummyU17
SC_IO1 / X1in491.8Vinternal cpld RGPIO CLKU17
SC_IO2 / X2out481.8Vinternal cpld RGPIO TXU17
SC_IO3 / X3in471.8Vinternal cpld RGPIO RXU17
SC_IO4 / X4out451.8VSD WP to slave cpldU17
SC_IO5 / X5in441.8VSTM dummyU17
SC_IO6 / X6out431.8V/ currently_not_usedU17
SC_IO7 / X7out421.8V/ currently_not_usedU17
SC_IO8 / X8in223V3SBinternal cpld RGPIO available(1.8V on)U17
SC_SCL / SCLin143V3SBI2C Mux U27 / currently_not_usedU17
SC_SDA / SDAin133V3SBI2C Mux U27 / currently_not_usedU17
SC2_SW3 / SW3in63V3SBDIP-Switch S5-3U17
SC2_SW4 / SW4in53V3SBDIP-Switch S5-4U17
SD_WPin1003V3SBMMC SD WPU17
SFP_LED1 / SFP_LED0out813V3SBSFPU17
SFP_LED2 / SFP_LED1out823V3SBSFPU17
SFP_LED3 / SFP_LED2out783V3SBSFPU17
SFP_LED4 / SFP_LED3out833V3SBSFPU17
SFP1_LOS
323V3SBSFP / currently_not_used U17
SFP1_TX_DISout333V3SBSFPU17
SFP2_LOS
353V3SBSFP / currently_not_used U17
SFP2_TX_DISout343V3SBSFPU17
STAT_LED0 / LED0out993V3SBLED D4 Green U17
STAT_LED1 / LED1out1283V3SBLED D1 Red U17
USB0_RST / USB_TRST
711.8VUSB (U9) PHY ResetU17
USBH_LED_G3
113V3SBUSB Hub (U4)  / currently_not_used U17
USBH_LED_G4
123V3SBUSB Hub (U4)  / currently_not_used U17
USBH_LED_SS1
93V3SBUSB Hub (U4)  / currently_not_used U17
USBH_LED_SS2
1333V3SBUSB Hub (U4)  / currently_not_used U17
USBH_LED_SS3
1323V3SBUSB Hub (U4)  / currently_not_used U17
USBH_LED_SS4
1383V3SBUSB Hub (U4)  / currently_not_used U17
USBH_MODE0out1423V3SBUSB Hub (U4)U17
USBH_MODE1out1433V3SBUSB Hub (U4)U17
USBH_RSTout103V3SBUSB Hub (U4)U17
XMOD1_A / XMOD_TXDout33V3SBJ28 (XMOD 2 UART)U17
XMOD1_B / XMOD_RXDin23V3SBJ28 (XMOD 2 UART)U17
XMOD1_E / XMOD_Eout43V3SBJ28 (XMOD 2 LED)U17
XMOD1_G / XMOD_Gout13V3SBJ28 (XMOD 2 Button)U17
1.8V_EN / EN_1V8out1063V3SBEnable 1.8V PowerU39
5V_EN / EN_5Vout1153V3SBEnable 5V Power, can be permanently enabled by S4-4U39
C_TCK
1313V3SBJTAG J28 (XMOD2)  / currently_not_used U39
C_TDOout1373V3SBJTAG J28 (XMOD2)
U39
C_TDO1 / C_TDIin1363V3SBJTAG J28 (XMOD2) U39
C_TMS
1303V3SBJTAG J28 (XMOD2)  / currently_not_used U39
CLK_A / AUD_CLKout11.8VAUDIO U3 CLKU39
CLK_CPLD / MEMS_CLKINin1283V3SBU25 24,576MHzU39
DONEin671.8VPS DoneU39
EN_DDRout863V3SBEnable Module DDR PowerU39
EN_FMC / FMC_ENout1043V3SBFMCU39
EN_FPDout813V3SBEnable Module PS FPD PowerU39
EN_GT_Lout773V3SBEnable Module GT PowerU39
EN_GT_Rout933V3SBEnable Module GT PowerU39
EN_LPDout843V3SBEnable Module  PS LPD PowerU39
EN_PLout953V3SBEnable Module PL PowerU39
EN_PLL_PWRout783V3SBEnable Module SI5345 PowerU39
EN_PSGT / EN_PSGTRout753V3SBEnable Module PS GT PowerU39
ERR_OUT / ERRORin701.8VModule PS Error Out / StatusU39
ERR_STATUS / ERR_STATin691.8VModule PS Error StatusU39
F1PWMout1213V3SBFAN1U39
F1SENSEin1253V3SBFAN1U39
FAN_FMC_EN / FMC_FAN_EN
1323V3SBFMC FANU39
FMC_PG_C2Mout1413V3SBFMC PGU39
HD_LED_N / HDLED_Nout1123V3SBJ10 HD LEDU39
HD_LED_P / HDLED_Pout1103V3SBJ10 HD LEDU39
HDIO_SC0 / SC0in321.8VFPGA IO /  forward to HD_LED_P / HDLED_PU39
HDIO_SC1 / SC1in331.8V/ currently_not_used U39
HDIO_SC2 / SC2in341.8V/ currently_not_used U39
HDIO_SC3
351.8V / currently_not_used U39
HDIO_SC4
251.8V / currently_not_used U39
HDIO_SC5 / SC5out261.8VFPGA IO / RGPIOU39
HDIO_SC6 / SC6in271.8VFPGA IO / RGPIO CLKU39
HDIO_SC7 / SC7in281.8V.FPGA IO / RGPIOU39
I2C_SCL / SCLin501.8VI2C / currently_not_usedU39
I2C_SDA / SDAin521.8VI2C / currently_not_usedU39
INIT_B / INITin681.8VModule PS Init_BU39
JTAGENB
1203V3SBexternal Pin for CPLD Firmware UpdateU39
LP_GOOD / PG_LPDin833V3SBModule LP Power GoodU39
MIO24
381.8VMIO  / currently_not_used U39
MIO25
391.8VMIO  / currently_not_used U39
MIO30in481.8VMIO / USB ResetU39
MIO31in491.8VMIO / PCIe ResetU39
MIO32
401.8VMIO / currently_not_used U39
MIO33
411.8VMIO  / currently_not_used U39
MIO34
421.8VMIO  / currently_not_used U39
MIO35
431.8VMIO  / currently_not_used U39
MIO36
441.8VMIO  / currently_not_used U39
MIO37
451.8VMIO  / currently_not_used U39
MIO40in541.8VMIOU39
MIO41
551.8VMIO  / currently_not_used U39
MIO42out601.8VMIOU39
MIO43in611.8VMIOU39
MIO44
471.8VMIOU39
MOD_ENout1193V3SBEnable Main Module Power 3.3VU39
MODE0out61.8VModule Boot ModeU39
MODE1out91.8VModule Boot ModeU39
MODE2out101.8VModule Boot ModeU39
MODE3out111.8VModule Boot ModeU39
MR / MRESETnout923V3SBModule PS Power ResetU39
PCI_SFP_ENout763V3SBSFPU39
PER_ENout1173V3SBEnable 3.3V powerU39
PERST / PERSTnout1393V3SBPCIE ResetnU39
PG_DDRin913V3SBModule Power GoodU39
PG_FPDin853V3SBModule Power GoodU39
PG_GT_Lin963V3SBModule Power GoodU39
PG_GT_Rin943V3SBModule Power GoodU39
PG_PLin823V3SBModule Power GoodU39
PG_PLL_1V8 / PG_PLLin733V3SBModule Power GoodU39
PG_PSGTin743V3SBModule Power GoodU39
PLL_LOLn / PLL_LOLin581.8VModule PLL / currently_not_usedU39
PLL_RST / PLL_RSTnout561.8VModule PLL ResetU39
PLL_SEL0out571.8VModule PLLU39
PLL_SEL1out591.8VModule PLLU39
POK_1V8in1073V3SBCarrier Power GoodU39
POK_FMCin993V3SBFMC Power GoodU39
PROG_BOUT711.8VModule PS_PROG_BU39
PSONout1053V3SBATX J20 PS_ON_NU39
PWR_BTNin1133V3SBPower Button S1 or J10U39
PWRLED_N / LED_Nout1113V3SBJ10 PWRU39
PWRLED_P / LED_Pout1093V3SBJ10 PWRU39
PWROKin1003V3SBATX J20 PWROKU39
RST_BTNin1143V3SBReset Button S2 or J10U39
S_1
1273V3SBBEEPER / currently_not_used U39
SC_IO0 / X0in121.8VMTS dummyU39
SC_IO1 / X1out131.8Vinternal cpld RGPIO CLKU39
SC_IO2 / X2in141.8Vinternal cpld RGPIO RXU39
SC_IO3 / X3out201.8Vinternal cpld RGPIO TXU39
SC_IO4 / X4in211.8VMMC SD WP from masterU39
SC_IO5 / X5out221.8VSTM dummyU39
SC_IO6 / X6in231.8V / currently_not_used U39
SC_IO7 / X7in241.8V / currently_not_used U39
SC_IO8 / X8out1263V3SBinternal cpld RGPIO available(1.8V on)U39
SC2_SW1 / SW1in1333V3SBS5-1 / Boot Mode SelectionU39
SC2_SW2 / SW2in1383V3SBS5-2 / Boot Mode SelectionU39
SD_A_ENout1403V3SBMicro SDU39
SD_B_ENout1223V3SBMMC SDU39
SD_CD / SD_CD_OUTout651.8VSD Card detect to FPGAU39
SD_CD_Bin1433V3SBMMC SD CDU39
SD_CD_Sin1423V3SBMicro SD CDU39
SEL_SD / SD_SELout621.8VSD select (Mirco or MMC)U39
SRST_B / SRSTnout191.8VModule PS_SRST_BU39
STAT_LED2 / LED2out983V3SBLED D6 GreenU39
STAT_LED3 / LED3out973V3SBLED D7 RedU39
XMOD2_A / XMOD_TXDout51.8VJ12 (XMOD 1 UART)U39
XMOD2_B / XMOD_RXDin41.8VJ12 (XMOD 1 UART)U39
XMOD2_E / XMOD_LEDout31.8VJ12 (XMOD 1 LED)U39
XMOD2_G / XMOD_BTNin21.8VJ12 (XMOD 1 Button)U39

Functional Description

JTAG

JTAGENB set carrier board CPLD into the chain for firmware update. For Update set DIP S4-3 to ON.

Power

FMC VADJ is handled on master CPLD.

DIPPositonDescription
S5-4ON1.8V
S5-4OFF1.2V

Power on and off sequencing is done with slave CPLD.

Power On/OFF Sequencing

Note: Power downs sequencing above can be disabled with second optional CPLD Firmware:

  1. Configure Firmware version SCM_07B_powerdown_disabled.jed/SCS_07B_powerdown_disabled.jed
  2. Add Jumper to J10-6 and J10-8 instead of Enclousure Button
  3. Module will be powered and boot on with Main power supply.

Reset

Power, Zynq reset and PCIe is handle on Slave CPLD

USB, I2C Reset is handled on Master CPLD

Type controlled by
PCiePower On Reset_N(pwr_rdy), MIO31
USB(PHY+HUB)Power On Reset_N(pwr_rdy), MIO30
Modul PLLPower On Reset_N(pwr_rdy)
PS_POR_BReset Button (hold long time ~3s), zynq_reset_ready
PS_SRST_BReset Button (hold short time ~1s), zynq_reset_ready
FMC_FAN_ENPower On Reset_N(pwr_rdy)
I2C_RSTPower On Reset_N(pwr_rdy)
ETH_RSTPower On Reset_N(pwr_rdy)


JTAG

CPLD JTAG only needed for CPLD Firmware update.

FMC and CPLD JTAG is accessable over XMOD2(J28).

S4-3
ONCPLD Access on both CPLD
OFFFMC JTAG Access

PJTAG on connector J17 is routed over Master CPLD to MIO26..29.

SignalConnection
JTAG_TCKMIO26
JTAG_RTCKJTAG_TCK
JTAG_TDIMIO27
JTAG_TDOMIO28
JTAG_TMSMIO29
JTAG_SRSTnot usedconnected only to FPGA RGPIO
JTAG_TRSTnot used, connected only to FPGA RGPIO

Boot Mode

Boot Mode is handled on Slave CPLD.

S5-1S5-2Description
ONONDefault, boot from SD/microSD or SPI Flash if no SD is detected
OFFONBoot from eMMC
ONOFFBoot mode PJTAG0
OFFOFFBoot mode main JTAG

Note: There is a second CPLD Variant available, where microSD will not change the boot mode.

  1. Configure Firmware version SCM_07C_msdboot_disabled.jed/SCS_07C_msdboot_disabled.jed
  2. Boot mode will be still QSPI,when microSD is insered.

PCIe

PCIe is handled on Slave CPLD.

SignalConnection
PERSTnPower On reset and MIO31

SD

SD is mainly handled on Slave CPLD

SD SignalDescription
SD_SELCD Pin form microSD selects the SD Card, microSD has higher priority
CD (MIO45)mircoSD and SD Card detect
WP(MIO44)0 when miroSD is used else SD card detect (forrward over Master CPLD)

UART SoC

SoC(ZynqMP) is accessible over XMOD1(J12) and connected to ZynqMP over Slave CPLD

SignalDescription
XMOD_TXDZynqMP TX(MIO43), when PWR Ready else 1
XMOD_RXDto ZynqMP RX(MIO42), when PWR Ready else 1

UART (Debug)

Simple Firmware Debug UART is accessible over XMOD2(28) over Master CPLD

Firmware Versions and some statistics can be displayed over second XMOD:

  • Included since CPLD Firmware Update to REV07
  • UART Speed is 115200
  • Press XMOD Button to see output, otherwise RX/TX are loop backed
SignalDescription
XMOD_TXDDebug output, when XMOD Button is pressed else RX loopback
XMOD_RXDDebug input(currently no function), when XMOD Button is pressed else TX loopback

CAN

CAN  is handled mainly on Master CPLD

SignalDescription
CAN_TXSC18(FPGA LOC depends on module)
CAN_RXSC19(FPGA LOC depends on module)
CAN_SSC16(FPGA LOC depends on module)
CAN_FAULTMonitoring over RGPIO only

USB

USB Reset is handled mainly on Master CPLD

SignalDescription
USB_RSTPower On Reset and MIO30 (over slave CPLD)
USBH_RSTPower On Reset and MIO30 (over slave CPLD)
USBH_MODE0const 1
USBH_MODE1const 1

DisplayPort

DisplayPort is handled on Master CPLD

SignalDescription
DP_ENnot Power On Reset
DP_RXto SC10 when SC11 is 0 else Z
DP_TXSX10
DP_DESC11
DP_HPDSC12

SFP

ETH Reset is handled on Master CPLD

SignalDescription
SFP1_TX_DISconst 0 (Enabled)
SFP2_TX_DISconst 0 (Enabled)

I2C

I2C MUX is handled on Master CPLD

SignalDescription
I2C_RSTPower On Reset

ETH

ETH Reset is handled on Master CPLD

SignalDescription
ETH_RSTPower On Reset
PHY_CONFIGconst 1

LEDs

LEDs are handled on both CPLDs.

They used different Blink Sequence to indicate all state:

******** (slow blinking)~0,7 Hzcontinuous blinking, like SFP LEDs or Enclosure HD LED when board is powered down
******** (fast blinking)~5,8 Hzcontinuous blinking, like D6 LED or Enclosure Power LED when board is powered down
*****ooo~0,7 Hz, duty cycle 5/85 times fast blink with a break
****oooo~0,7 Hz, duty cycle 4/84 times fast blink with a break
***ooooo~0,7 Hz, duty cycle 3/83 times fast blink with a break
**oooooo~0,7 Hz, duty cycle 2/82 times fast blink with a break
*ooooooo~0,7 Hz, duty cycle 1/81 times fast blink with a break
ON---LED ON
OFF---LED OFF


DesignatorColorUsageDescription
D7Redstatus
PriorityDescriptionBlink sequencing
1PS POR Reset pressed long time (or whole system is powered off)ON
2PS Soft Reset pressed short timeOFF
3SD Boot*ooooooo
4QSPI Boot**oooooo
5eMMC Boot***ooooo
6PJTAG Boot****oooo
7JTAG Boot*****ooo
8Error******** (fast blinking)
D6Greenstatus
PriorityDescriptionBlink sequencing
1Power OFF******** (fast blinking)
2PG_LPD low*****ooo
3PG_FPD low****oooo
4PG_PL low***ooooo
5PG_DDR low or PG_PSGT low or PG_PLL low or PG_GT_L low or PG_GT_R low**oooooo
6POK_1V8 low or POK_FMC low or perihpery_pg low or (Main Power State Machine Ready and FMC Sanity check low)*ooooooo
7Main Power State Machine ReadyOFF
8ERROR some power failed, see XMOD LEDsON
J10 Power LEDBlue (symbol light bulb)status/user
PriorityDescriptionBlink sequencing
1power button pressed long time forced power down******** (fast blinking)
2

Main Power State Machine Idle and Power of State is off

******** (slow blinking)
3power button pressed short time power to power on/off*****ooo
4PS reset button pressed long time****oooo
5PS reset button pressed short time***ooooo
6power down sequencing is running**oooooo
7whole system hold into reset*ooooooo
8MIO40User Defined
J10 HD LED

Red (symbol drive)

status/user
PriorityDescriptionBlink sequencing
1PS Init is low******** (fast blinking)
2PS Error High*****ooo
3PS Error Status High****oooo
4SOC Done  low***ooooo
5SC0User Defined
XMOD1 D4Redstatus
PriorityXMOD ButtonDescriptionBlink sequencing
1Pressedpower button pressed long time forced power down******** (fast blinking)
2PressedMain Power State Machine Idle and Power of State is power down
sequencing
*****ooo
3Pressed

PS reset button pressed

****oooo
4PressedPower button pressed short time power on/off***ooooo
5PressedPower of State is power down sequencing**oooooo
6PressedSystem hold into reset*ooooooo
7PressedPS Init lowON
1UnpressedProblem with other CPLD, FMC is disabled******** (fast blinking)
2UnpressedMain Power State Machine Wait Ready ON/OFF*****ooo
3UnpressedMain Power State Machine 3.3V and VADJ ON/OFF****oooo
4Unpressedpower not ready (power reset)**oooooo
5Unpressedzynq reset*ooooooo
7UnpressedPS Init lowON
xPressed/Unpressedall fineOFF
XMOD2 D4Redstatus/user
PriorityDescriptionBlink sequencing
1Power On Reset********  (slow blinking)
2PS Init low******** (fast blinking)
3SC17User Defined
SFP D1Redstatus/user
PriorityDescriptionBlink sequencing
1Power On Reset******** (slow blinking)
2PS Init low******** (fast blinking)
3RGPIO(0), when RGPIO Enabled over FPGAUser Defined
4--OFF
SFP D8Greenstatus/user
PriorityDescriptionBlink sequencing
1Power On Reset******** (slow blinking)
2PS Init low******** (fast blinking)
3RGPIO(1), when RGPIO Enabled over FPGAUser Defined
4--OFF
D17 - USB HUB LED (Suspend)GreenstatusON, no USB connected, OFF, USB connected
SFP D9Redstatus/user
PriorityDescriptionBlink sequencing
1Power On Reset******** (slow blinking)
2PS Init low******** (fast blinking)
3RGPIO(2), when RGPIO Enabled over FPGAUser Defined
4--OFF
SFP D10Greenstatus/user
PriorityDescriptionBlink sequencing
1Power On Reset******** (slow blinking)
2PS Init low******** (fast blinking)
3RGPIO(3), when RGPIO Enabled over FPGAUser Defined
4--OFF
ETH J7Yellowstatus
PriorityDescriptionBlink sequencing
1Power On Reset******** (slow blinking)
2PS Init low******** (fast blinking)
3ETH PHY LED(not PHY_LED0)
ETH J7Green/Orangestatus
PriorityDescriptionBlink sequencing
1Power On Reset******** (slow blinking)
2PS Init low******** (fast blinking)
3ETH PHY LED(PHY_LED1)
D4Greenstatus/user
PriorityDescriptionBlink sequencing
11.8V disabled, inter CPLD RGPIO is disabled******** (fast blinking)
21.8V enabled, inter CPLD RGPIO is disabled*****ooo
3Power On Reset****oooo
4USB Reset***ooooo
5RGPIO(4), when RGPIO Enabled over FPGAUser Defined
6all fine*ooooooo
D5Redstatus/user
PriorityDescriptionBlink sequencing
11.8V disabled, inter CPLD RGPIO is disabled******** (fast blinking)
21.8V enabled, inter CPLD RGPIO is disabled*****ooo
3Power On Reset****oooo
4PCie Reset***ooooo
5RGPIO(4), when RGPIO Enabled over FPGAUser Defined
6all fine*ooooooo


RGPIO 

There are 3 RGPIO interfaces, one InterCPLD RGPIO, and one from every CPLD to SoC.

InterCPLD RGPIO handles:

SignalDescription
Reset Button (SW)for monitoring only
PS PORfor monitoring only
PS ERR Statfor monitoring only
PS ERRfor monitoring only
PS Initfor monitoring only
PCIe Resetfor monitoring only
USB Resetfor USB Reset and monitoring
Power On Resetfor Power On Reset and monitoring
inter FPGAData from Slave RGPIO to Master RGPIO (for test only)


Master CPLD-SoC RGPIO (accesseble via SoC):

SignalDescription
FPGA Read (23)JTAG_SRST
FPGA Read (22)JTAG_TRST
FPGA Read (21)FMC_CLKDIR
FPGA Read (20)SD_WP
FPGA Read (19)unused 0
FPGA Read (18)SW4
FPGA Read (17)SW3
FPGA Read (16)XMOD_G
FPGA Read (15 dt 13)PHY LEDs
FPGA Read (12)CAN_FAULT
FPGA Read (11 dt 8)current RGPIO Mux
FPGA Read (7 dt 0)

Data depends on MUX:

0Data(7dt0) from Slave CPLD-SoC RGPIO
1POR Statistic
2PS RST Statistic
3PS POR Statistic
4PS Init Statistic
5PS ERR Statistic
6PS ERR Stat Statistic
7PCie RST Statistic
8USB RST Statistic
FPGA Write (23 dt 12)unused
FPGA Write (11 dt 8)RGPIO Mux, see FPGA Read (7 dt 0) , when RGIO active
FPGA Write (7 dt 6)unused
FPGA Write (5 dt 0)Diverse LED controll(see LED description) , when RGIO active

Slave CPLD-SoC RGPIO (accesseble via SoC):

SignalDescription
FPGA Read (23)PLL_LOL
FPGA Read (22)PG_PLL
FPGA Read (21)PG_PL
FPGA Read (20)PWROK and pwrok_force_zero_n
FPGA Read (19)fmc_sanity_check
FPGA Read (18)POK_FMC
FPGA Read (17)PG_GT_R
FPGA Read (16)PG_GT_L
FPGA Read (15)PG_PSGT
FPGA Read (14)PG_FPD
FPGA Read (13)PG_DDR
FPGA Read (12)PG_LPD
FPGA Read (11 dt 8)current Boot Mode
FPGA Read (7)ERR_STAT
FPGA Read (6)ERROR
FPGA Read (5)SD_CD_B
FPGA Read (4)SD_CD_S
FPGA Read (3)unused const 1
FPGA Read (2)XMOD_BTN
FPGA Read (1)SW2
FPGA Read (0)SW1
FPGA Write (23 dt 8)unused
FPGA Write (7dt 0)Readable over Master CPLD-SoC RGPIO, when RGIO active

Appx. A: Change History and Legal Notices

Revision Changes

MasterSlave

CPLD REV01 to TEBF0808 version

  • disable DP-HPD pullup
  • changed CPLD string name
  • counter deep for status register (otherwhise new version of lattice mapping tool has problems)

Copy from TEBF0808 SCB0808 REV07(dev)

CPLD REV01 to TEBF0808 version

  • Add Parameter to disable PWOK usage(for 12V only usage, CPLD can't detect which power supply is used on PCB REV01 and POWK will be forced to low, in case ATX is not connected)
  • PSON inverted

Copy from TEBF0808 SCB0808 REV07(dev)

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

v.2




REV01REV01*
  • Initial release (copy from TEBF0808 CPLD Firmware REV07  )
  • REV01 finished (Firmware released on 2021-09-21)
  • *special Firmware for TEBF0818-01 only

All


Legal Notices

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Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

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Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

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RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

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