Table of contents
Firmware for PCB-Master CPLD with designator U5: LCMX02-1200HC.
- Power Management
- Reset Management
- FMC JTAG
- LED Control
- FAN Control (FPGA)
- FAN Control (FMC
- I2C MUX
Firmware Revision and supported PCB Revision
See Document Change History
|Name / opt. VHD Name||Direction||Pin||Description||Connection changes compared to REV01|
|200MHZCLK_EN||out||30||Enable 200MHz Osc.|
|CPLD_JTAG_TCK||in||91||optional FMC JTAG|
|CPLD_JTAG_TDI||in||94||optional FMC JTAG|
|CPLD_JTAG_TDO||out||95||optional FMC JTAG|
|CPLD_JTAG_TMS||in||90||optional FMC JTAG|
|DDR3_SCL||inout||43||I2C connected to FPGA|
|DDR3_SDA||inout||42||I2C connected to FPGA|
|F1SENSE||in||99||FAN / currently_not_used|
|FEX0||out||12||PERST from PCIe slot|
|FAN_FMC_EN||out||78||FMC FAN Enable||not connected on REV01|
|FMC_PRSNT||in||40||FMC Present (inverted FMC_PRSNT_M2C_L )||not connected on REV01|
|N.C.||70||Not Connected||FMC_PRSNT_M2C_L on REV01|
|FMC_SCL||49||I2C connected to FPGA|
|FMC_SDA||48||I2C connected to FPGA|
|JTAG_EN||in||82||JTAG ENABLE over DIP S1-1||constant high on REV01|
|LED1||out||76||Status LED D1 (green)|
|LTM_SCL||67||I2C connected to FPGA|
|LTM_SDA||66||I2C connected to FPGA|
|PCIE_RSTB||in||37||PERST from PCIe card edge connector|
|VID0_FMC_VADJ||out||53||FMC EN5365QI power selection pin|
|VID0_FMC_VADJ_CTRL||in||71||Power pin pre-selection for FMC VADJ through DIP SW S1-2. CPLD decides.||not connected on REV01|
|VID1_FMC_VADJ||out||54||FMC EN5365QI power selection pin|
|VID1_FMC_VADJ_CTRL||in||63||Power pin pre-selection for FMC VADJ through DIP SW S1-3. CPLD decides.||not connected on REV01|
|VID2_FMC_VADJ||out||57||FMC EN5365QI power selection pin|
|VID2_FMC_VADJ_CTRL||in||62||Power pin pre-selection for FMC VADJ through DIP SW S1-4. CPLD decides.||not connected on REV01|
CPLD JTAG is selectable with DIP S1-1. (ON FMC, OFF CPLD).
FMC JTAG is accessible with J9 JTAG Pinheader on PCB REV02 and newer only.
Power sequence on will be executed over 4 States:
- State 1 IDLE: Wait until LTM_1V_IO0 (1V), LTM_1V_IO1 (1V) and LTM_1V5_4V_IO1 (4V) is available.
- State 2 PS1: Enables 1V8, 3V3FMC and VADJ. Wait until PG_1V8 (1.8V), PG_3V3 (3.3V) and PG_FMC_VADJ (FMC VADJ) is available.
- State 3 PS2: Wait until LTM_1V5_4V_IO0 (1.5V) is available
- State 4 RDY: All power on
State machine restart power sequencing, if on of the power good signal are lost.
FMC VADJ is selectable via DIP S1-2...4.
Note on PCB REV01 it's fix 1.8V.
PROGRAM_B is controlled by push button after power up sequencing is ready.
200MHz CLK is enabled after power up.
Connect SI5338, LTM and FMC, SODIMM I2C and internal FAN Control to FPGA I2C Bus.
I2C Baseaddress: 0x74 (changeable with Firmware update). I2C with 8Bit Register Address with 8Bit Data. I2C CLK currently 20 MHz supported.
|0||FAN CTRL||Enable FAN1 (Bit7)|
|1||FAN1 PWM||FAN1 PWM (0%-100%, Default 80%)|
|0||FAN CTRL||FAN Control register|
|1||FAN1 RPS||FAN1 Revolutions per second|
Is enabled/disabled with FMC preset signal (PCB REV02 only).
Button is debounced and controls PROG_B signal from FPGA.
LED is used as Status LED for power management and programming. Status depends on blink sequence.
|Error - Power IDLE state||********||Reset or Main Power Problem|
|Error - Power PS1 state||*****ooo||Periphery Power Problem (1.8V, 3.3V, FMC VADJ)|
|Error - Power PS2 state||****oooo||DDR Bank Power Problem (1.5V)|
|Power Ready, FPGA not programmed||***ooooo||~0,7 Hz, duty cycle 3/8|
|--||**oooooo||~0,7 Hz, duty cycle 2/8, currently not used|
|--||*ooooooo||~0,7 Hz, duty cycle 1/8, currently not used|
|User Mode||user defined||Power Ready, FPGA programmed, LED is accessible over FEX11|
Appx. A: Change History and Legal Notices
CPLD REV02 to REV03
- FMC JTAG access over CPLD Programmer (not accessible on PCB REV01)
- DIP VADJ (not usable on PCB REV01)
- FMC FAN EN/DIS over FMC_PRSNT (not usable on PCB REV01)
CPLD REV01 to REV02
- BUGFIX: PCIe Reset
- USER LED accessible
- I2C for SI5338, LTM, FMC, SODIMM
- Add FAN Control over I2C
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
|Date||Document Revision||CPLD Firmware Revision||Supported PCB Revision||Authors||Description|
Appx. A: Legal Notices
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