Table of contents
Firmware for PCB-Master CPLD with designator U5: LCMX02-1200HC.
- Power Management
- Reset Management
- LED Control
- FAN Control
- I2C MUX
Firmware Revision and supported PCB Revision
See Document Change History
|Name / opt. VHD Name||Direction||Pin||Description|
|CPLD_JTAG_TCK||91||not accessible as IO|
|CPLD_JTAG_TDI||94||not accessible as IO|
|CPLD_JTAG_TDO||95||not accessible as IO|
|CPLD_JTAG_TMS||90||not accessible as IO|
|DDR3_SCL||inout||43||I2C connected to FPGA|
|DDR3_SDA||inout||42||I2C connected to FPGA|
|F1SENSE||in||99||FAN / currently_not_used|
|FEX0||out||12||PERST from PCIe slot|
|FMC_SCL||49||I2C connected to FPGA|
|FMC_SDA||48||I2C connected to FPGA|
|LED1||out||76||Status LED D1 (green)|
|LTM_SCL||67||I2C connected to FPGA|
|LTM_SDA||66||I2C connected to FPGA|
|PCIE_RSTB||in||37||PERST from PCIe card edge connector|
|VID0_FMC_VADJ||out||53||FMC EN5365QI power selection pin|
|VID1_FMC_VADJ||out||54||FMC EN5365QI power selection pin|
|VID2_FMC_VADJ||out||57||FMC EN5365QI power selection pin|
CPLD JTAG is always enabled.
Power sequence on will be executed over 4 States:
- State 1 IDLE: Wait until LTM_1V_IO0 (1V), LTM_1V_IO1 (1V) and LTM_1V5_4V_IO1 (4V) is available.
- State 2 PS1: Enables 1V8, 3V3FMC and VADJ. Wait until PG_1V8 (1.8V), PG_3V3 (3.3V) and PG_FMC_VADJ (FMC VADJ) is available.
- State 3 PS2: Wait until LTM_1V5_4V_IO0 (1.5V) is available
- State 4 RDY: All power on
State machine restart power sequencing, if on of the power good signal are lost.
FMC VADJ is set to 1.8V.
PROGRAM_B is controlled by push button after power up sequencing is ready.
200MHz CLK is enabled after power up.
Connect SI5338, LTM and FMC, SODIMM I2C and internal FAN Control to FPGA I2C Bus.
I2C Baseaddress: 0x74 (changeable with Firmware update). I2C with 8Bit Register Address with 8Bit Data. I2C CLK currently 20 MHz supported.
|0||FAN CTRL||Enable FAN1 (Bit7)|
|1||FAN1 PWM||FAN1 PWM (0%-100%, Default 80%)|
|0||FAN CTRL||FAN Control register|
|1||FAN1 RPS||FAN1 Revolutions per second|
Button is debounced and controls PROG_B signal from FPGA.
LED is used as Status LED for power management and programming. Status depends on blink sequence.
|Error - Power IDLE state||********||Reset or Main Power Problem|
|Error - Power PS1 state||*****ooo||Periphery Power Problem (1.8V, 3.3V, FMC VADJ)|
|Error - Power PS2 state||****oooo||DDR Bank Power Problem (1.5V)|
|Power Ready, FPGA not programmed||***ooooo||~0,7 Hz, duty cycle 3/8|
|--||**oooooo||~0,7 Hz, duty cycle 2/8, currently not used|
|--||*ooooooo||~0,7 Hz, duty cycle 1/8, currently not used|
|User Mode||user defined||Power Ready, FPGA programmed, LED is accessible over FEX11|
Appx. A: Change History and Legal Notices
CPLD REV01 to REV02
- BUGFIX: PCIe Reset
- USER LED accessible
- I2C for SI5338, LTM, FMC, SODIMM
- Add FAN Control over I2C
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
|Date||Document Revision||CPLD Firmware Revision||Supported PCB Revision||Authors||Description|
Appx. A: Legal Notices
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