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Overview

TEF1002 SC CPLD design for MAX10 with designator U11:  10M08SAU169C8G.

Feature Summary

  • Power Management
    • SATA pin 7 power control
  • Status LED
  • FMC VADJ Power
  • SFP control
  • FFA & FFB control
  • JTAG MUX
  • Module control
  • RESET
  • I2C MUX
  • PHY LEDs
  • RGPIO
  • USR LED

Firmware Revision and supported PCB Revision

See Document Change History.

Product Specification

Port Description

VHDL Port nameDirectionSC CPLD PinConnected toFunctionNotes
ACBUS0
A4FTDI U4, pin 22GPIO's available to user











currently not used/implemented

(FIFO or other FTDI functions when FTDI reprogrammed)











ACBUS1
B4FTDI U4, pin 23
ACBUS2
A5FTDI U4, pin 24
ACBUS3
B5FTDI U4, pin 25
ACBUS4
A6FTDI U4, pin 26
ACBUS5
B6FTDI U4, pin 27
ACBUS6
A7FTDI U4, pin 28
ACBUS7
A8FTDI U4, pin 29
ADBUS4
A2FTDI U4, pin 17
ADBUS5
B2FTDI U4, pin 18
ADBUS6
A3FTDI U4, pin 19
ADBUS7
B3FTDI U4, pin 20
P_TCKING2J5, pin 1JTAG signals from pin header J5 for SC CPLD programming (S2-4 ON)



Can be used as additional IOs via JTAG pinsharing, JTAGEN (S2-4 OFF). Schematic signal names without 'P_'.


P_TDIINF5J5, pin 9
P_TDOOUTF6J5, pin 3
P_TMSING1J5, pin 5
F_TCKINH2FTDI U4, pin 12Forwarded JTAG signals from FTDI chip. Signal names: TCK, TDI, TDO, TMS(FIFO or other FTDI functions when FTDI reprogrammed)
F_TDIING4FTDI U4, pin 13
F_TDOOUTF4FTDI U4, pin 14
F_TMSINH5FTDI U4, pin 15
M_TCKOUTH5JB2, pin 1004x5 Module JTAG



Bank with VCCIO is VREF_JTAG from Module



M_TDIOUTJ2JB2, pin 96
M_TDOINJ1JB2, pin 98
M_TMSOUTH6JB2, pin 94
FMC_TCKOUTF8J1, pin D29FMC JTAG




TRST not used



FMC_TDIOUTM7J1, pin D30
FMC_TDOINN7J1, pin D31
FMC_TMSOUTM8J1, pin D33
FMC_TRST
N8J1, pin D34
PCIE_TCK
L11J3, pin A5PCIe JTAG




Currently not used




PCIE_TDI
N12J3, pin A6
PCIE_TDO
M12J3, pin A7
PCIE_TMS
M13J3, pin A8
PCIE_TRST
G10J3, pin B9
PCIE_PERSTINF12J3, pin A11Indication that PCIe Bus is up (power, clocks)
EN_FMCOUTL4U14, pin 9Enable switched 3.3V FMC powerpulled down
EN_FMC_VADJOUTK7U1, pin 41Enable IO power FMC_VADJpulled down
EN_PEROUTF13Q4, pin 5Enable perepherie power 3V3_PERpulled down
FAN_FMC_ENOUTK8Q1, pin 5Enable FMC FANfloating during configuration (no pull down)
FMC_PG_C2MOUTM5J1, pin D1Indicate that all FMC related powers are uppulled up
FMC_PRSNT_M2C_LINE9J1, pin H2Indicate if FMC installedLow when FMC present, CPLD weak pullup enabled
FMC_SCLOUTJ8J1, pin C31I2C 2-wire serial busMUX in CPLD
FMC_SDAINOUTF9J1, pin C30
PG_FMC_VADJINJ6U1, pin 35Indicate FMC VADJ power is up
FF_RSTLOUTB9J13, pin 6  and J18, pin 6Reset configurationBoth FF are resetted simultanously when pulled LOW
FFA_INTLINE8J13, pin 5Indicate interrrupt

LOW when fault condition, pulled up

FFA_MPRSINC10J13, pin 3Indicate FF Module installedLOW when Module present, pulled up
FFA_MSELOUTC9J13, pin 4Select attached FF ModulePull low to use I2C
FFA_SCLOUTD6J13, pin 8I2C 2-wire serial busMUX in CPLD
FFA_SDAINOUTE6J13, pin 7
FFB_INTLINA10J18, pin 5Indicate interrruptLOW when fault condition, pulled up
FFB_MPRSINA11J18, pin 3Indicate FF Module installedLOW when Module present, pulled up
FFB_MSELOUTB10J18, pin 4Select attached FF ModulePull low to use I2C
FFB_SCLOUTD8J18, pin 8I2C 2-wire serial busMUX in CPLD
FFB_SDAINOUTA9J18, pin 7
CPLD_IO_1INB12JB1, pin 88(M)IOs from 4x5 Module(M)IOs used for ETH PHY LEDs

CPLD_IO_2INA12JB1, pin 92(M)IOs from 4x5 Module
M10_RST
D1

TP22




Not used


M10_RX
E4TP24
M10_TX
E3TP23
EN1OUTD11JB1, pin 27Enable on module powerDepends on module, on some similar to reset.
MODEOUTB11JB1, pin 31Boot Mode selectionFor Zynq modules only. (LOW → SD, HIGH → primary QSPI)
NOSEQOUTE13JB1, pin 8Disable module CPLD power managementDepends on module. On some modules no extended CPLD power management avaialble.
PGOODINOUTC11JB1, pin 29Power good signal

This is only for monitoring, do not use as powerenable! Pulled up.

RESINOUTE12JB2, pin 17Module ResetAktive LOW
M3.3VOUTINM4JB2, pin 9 and 11Indicates module power is up

Used for perepherie power enable. Floating when no module installed (no pull down).

SFPA_LOSINM10J12, pin 8SFP signal lossHIGH indicates signal loss
SFPA_M-DEF0INF10J12, pin 6SFP modul absentHIGH when module physically absent
SFPA_RS0OUTN10J12, pin 7SFP rate select RXLOW for 1000BASE-SX, HIGH for 10GBASE-SR
SFPA_RS1OUTM11J12, pin 9SFP rate select TXLOW for 1000BASE-SX, HIGH for 10GBASE-SR
SFPA_SCLOUTL10J12, pin 5I2C 2-wire serial busMUX in CPLD
SFPA_SDAINOUTN9J12, pin 4
SFPA_TX_DISOUTM9J12, pin 3SFP transmitter disableHIGH disables transmitter
SFPA_TX_FAULTING9J12, pin 2Indicates SFP laser faultHIGH indicates fault
VID0_FMC_VADJOUTE10U1, pin 34FMC_VADJ Voltage selectChip internal pulled up


VID1_FMC_VADJOUTJ7U1, pin 33
VID2_FMC_VADJOUTL5U1, pin 32
VID0INK6S2-1For FMC_VADJ Voltage select





VID1INN5S2-2
VID2INN4S2-3
FMC_JTAGINL3S2-6Select FMC JTAG port
CM0INM3S2-7SoM enable power
CM1INL2S2-8SoM Bootmode
CM2INK2S3-1disable SoM pwersequenzing
USR0INK1S3-2FMC VADJ power enablealso if no FMC installed
USB_OCIND9U12, pin 5

EN_5VSATAOUTE1U15, pin 1Enable/Disable SATA pin 7 power
OC_VSATAINF1U15, pin 2Overcurrent detection SATA pin 7 power
BUTTONINN6S1Module reset button
SD-CDINM1J8, pin 9SD-Card card detect switchCurrently not used
LED1OUTJ5D1user LED
LED2OUTK5D2
LED_D4OUTC2D4Status LED
PHY_LED1OUTD12J9Phy LEDs







PHY_LED1ROUTC13J9
PHY_LED2OUTB13J9
PHY_LED2ROUTC12J9
A_00_NINJ10JB1, pin 38SDA IN "three wire" I2C
A_00_PINK10JB1, pin 36SCL IN"three wire" I2C
A_01_NOUTL12JB1, pin 35TX dataRGPIO
A_01_POUTK11JB1, pin 37SDA OUT"three wire" I2C
A_02_NINJ12JB1, pin 41RX CLKRGPIO
A_02_PINK12JB1, pin 39RX dataRGPIO
A_03_N
H10JB1, pin 44Module to CPLD communicationcurrently not used
A_03_P
J9JB1, pin 42
A_04_N
H13JB1, pin 47
A_04_P
J13JB1, pin 45
A_05_PINH9JB1, pin 55
A_05_NINH8JB1, pin 57PHY LEDsHave to be Forwarede on SoM to this pins.
A_06_PING13JB1, pin 51
A_06_NING12JB1, pin 49I2C GPIO MUX 0I2C MUX also used for FireFlys MSEL
A_07INL13JB1, pin 34I2C GPIO MUX 1
SC CPLD ports

Functional Description

Power Management

The M3_3VOUT rail of the attached SoM is used to power up the powerrails on TEF1002. further dependencies ar given in the table below:

Port/Signaldepends on (RGPIO not aktive)additional when RGPIO aktiveDescriptionRemark
EN_PERM3_3VOUTrgpio_out_data_i(15)Enable perepherie power 3V3_PERvia PWR_EN_Signal
FMC_PWR_setM3_3VOUTrgpio_out_data_i(16)Signal indicate FMC enable
EN_FMCFMC_PWR_set and NOT(FMC_PRSNT_M2C_L)rgpio_out_data_i(17)Enable switched 3.3V FMC power
FAN_FMC_ENFMC_PWR_set and NOT(FMC_PRSNT_M2C_L) -Enable FMC FAN
EN_FMC_VADJ(FMC_PWR_set and NOT(FMC_PRSNT_M2C_L)) or (USR0 and FMC_PRSNT_M2C_L)-Enable IO power FMC_VADJUSR0 dip switch S3-2 can be used to enable FMC_VADJ when no FMC installed
EN5VSATA

if((OC_VSATA = '0') or (OC_SATA_DISABLED = '1'))then
   EN5VSATA <= '0';
   OC_SATA_DISABLED <= '1';
else
   EN5VSATA <= M3_3VOUT;
end if;

-Enable  5V SATA on pin 7Implemented with latch, when disabled, will be disabled until board power cycle.
FMC_PG_C2MFMC_PWR_set and NOT(FMC_PRSNT_M2C_L) and PG_FMC_VADJ-Indicate that all FMC related powers are up
Power Management

Status LED

The Status LED D4 is utilized in the following way:

Sequenz
Description
*ooooooo1 times fast blink with a breakSOM PGOOD fail
**oooooo2 times fast blink with a breaknot used
***ooooo3 times fast blink with a breakFMC power Error
****oooo4 times fast blink with a breakSATA pin 7 overcurrent ERROR
*****ooo5 times fast blink with a breakUSB Power Error
******oo6 times fast blink with a breakFirefly A or B Error
*******o7 times fast blink with a breakSFPA_TX_FAULT or SFPA_LOS
ONLED ONAll OK
Status LED description

FMC VADJ Power

Three of the dip switches are linked to the voltage selection signals of FMC_VADJ:


VID0, S2-1VID1, S2-2VID2, S2-3
3.3VOFFOFFOFF
2.5V

ON

OFFOFF
1.8VOFFONOFF
1.5V

ON

ONOFF
1.25VOFFOFFON
1.2V

ON

OFFON
0.8VOFFONON
FMC_VADJ selection

SFP control

SFP control signals are handled by RGPIO:

OUTPUTINPUTFunctionNotes
rgpio_in_data_i(19)SFPA_TX_FAULTTransmitter fault'high' when fault detected
rgpio_in_data_i(18)SFPA_MDEF0Module absent'high' when absent
rgpio_in_data_i(17)SFPA_LOSSignal Loss'high' when signal loss
SFPA_TX_DISrgpio_out_data_i(22)Transmitter disableDisable transmitter when 'high'
SFPA_RS0rgpio_out_data_i(21)Select recieve signal rate
SFPA_RS1rgpio_out_data_i(20)Select transmit signal rate
Connection SFP Control

FFA & FFB control

When RGPIO is aktive the FF resets are driven low via rgpio_out_data_i(23).

For FF I2C see I2C chapter. Module Present and Interrupt signals are forwarded to SoM via RGPIO ports:

OUTPUT to SoMSignal INPUTFunctionNotes
rgpio_in_data_i(23)FFA_MPRSModule presentaktive low
rgpio_in_data_i(22)FFB_MPRSModule presentaktive low
rgpio_in_data_i(21)FFA_INTLInterrupt outputOpen collector output driven low when an Interrupt occurs.
rgpio_in_data_i(20)FFB_INTLInterrupt outputOpen collector output driven low when an Interrupt occurs.
Connection FF Control

PCIE

The PCIexpress signal "PERST#" is forwarded to the SoM using signal CPLD_IO_1 (corresponding to B2B pin JB1-88).

      CPLD_IO_1 <= (PCIE_PERST and M3_3VOUT); -- forward PCIE PERST# to SOM

As long as RGPIO is not enabled, LED1 shows the inverted status of the PCIE_PERST signal (See USR LED).

JTAG MUX

The folowing table summarizes the JTAG MUX. Only FMC and SoM JTAG have to be handled in the CPLD explicitly. Discrimination between Module CPLD and Module SOC/FPGA are done via hard connected dip switch. Same is true for TEF1002 CPLD MAX10.

SignalJTAGEN S2-4M_JTAGEN S2-5FMC_JTAG S2-6
CPLD MAX 10 (header J5)

ON

DNCDNC
4x5 SoM CPLD (micro USB J10)DNCONOFF
4x5 SoC/FPGA (micro USB J10)DNCOFFOFF
FMC (micro USB J10)DNCDNCON
JTAG selection

Module control

The module control signals are connected to dip switches:

Signal OUTPUT to SoMSignal INPUTFunctionNotes
EN1CM0SoM enable power"high" when Dip ON. See SoM TRM for further description.
NOSEQCM1disable SoM powerseq"high" when Dip ON. See SoM TRM for further description.
MODECM2SoM Bootmode"high" when Dip ON. See SoM TRM for further description.
Connection SoM Control

RESET

The push button signal is connected to the RESIN signal of the SoM  (low active reset).

I2C and MUX

The SEL vector is used to select different I2C devices:

deviceSELNotes
SFPA00
FMC01
FFA10also used for FFA_MSEL
FFB11also used for FFB_MSEL
Connection I2C to SoM

A "three wire" I2C interface is used to connect the CPLD I2C  to the SoM:

VHDL Port nameDirectionSC CPLD PinConnected toFunctionNotes
A_00_NINJ10JB1, pin 38SDA IN "three wire" I2C
A_00_PINK10JB1, pin 36SCL IN"three wire" I2C
A_01_POUTK11JB1, pin 37SDA OUT"three wire" I2C
Connection I2C to SoM

The devices SDA are driven in the following way: DEVICE_XY_SDA <= '0' when SEL= "XY" and A_00_N='0' else 'Z';

The SDA to the SoM is generated by the logical AND connection of all devices:  SDAs <= (SFPA_SDA AND FMC_SDA AND FFA_SDA AND FFB_SDA )


VHDL Port nameDirectionSC CPLD PinConnected toFunctionNotes
FMC_SCLOUTJ8J1, pin C31I2C 2-wire serial busMUX in CPLD
FMC_SDAINOUTF9J1, pin C30
FFA_MSELOUTC9J13, pin 4Select attached FF ModulePull low to use I2C
FFA_SCLOUTD6J13, pin 8I2C 2-wire serial busMUX in CPLD
FFA_SDAINOUTE6J13, pin 7
FFB_MSELOUTB10J18, pin 4Select attached FF ModulePull low to use I2C
FFB_SCLOUTD8J18, pin 8I2C 2-wire serial busMUX in CPLD
FFB_SDAINOUTA9J18, pin 7
A_01_POUTK11JB1, pin 37SDA OUT"three wire" I2C
A_06_NING12JB1, pin 49I2C GPIO MUX 0I2C MUX also used for FireFlys MSEL
A_07INL13JB1, pin 34I2C GPIO MUX 1
SC I2C MUX ports

PHY LEDs

The following signals are used to drive the PHY LEDs.

Signal VHDLnameFunctionNotes
A_05_NPHY_LED1drive LEDConnected to JB1-57
net_gndPHY_LED1Rselect coloryellow
A_06_PPHY_LED2drive LEDConnected to JB1-51
net_gndPHY_LED2Rselect colorgreen
Connection of PHY LEDs

RGPIO

The RGPIO is for communiction betweenn SoC and SC CPLD it handels the signals:

Signal VHDLnameFunctionNotes
SoC write (23)FF_RSTLReset configurationBoth FF are resetted simultanously when pulled LOW
SoC write (22)SFPA_TX_DISSFP transmitter disableHIGH disables transmitter
SoC write (21)SFPA_RS0SFP rate select RXLOW for 1000BASE-SX, HIGH for 10GBASE-SR
SoC write (20)SFPA_RS1SFP rate select TXLOW for 1000BASE-SX, HIGH for 10GBASE-SR
SoC write (19)LED1user LEDs
SoC write (18)LED2
SoC write (17)EN_FMCEnable switched 3.3V FMC powerpulled down
SoC write (16)FMC_PWR_setTurn on FMC Powerused for EN_FMC_VADJ and FAN_FMC_EN
SoC write (15)PWR_EN_SignalEnable perepherie power 3V3_PERused for EN_PER
SOC read (23)FFA_MPRSIndicate FF Module installedLOW when Module present, pulled up
SOC read (22)FFB_MPRSIndicate FF Module installedLOW when Module present, pulled up
SOC read (21)FFA_INTLIndicate interrrupt

LOW when fault condition, pulled up

SOC read (20)FFB_INTLIndicate interrruptLOW when fault condition, pulled up
SOC read (19)SFPA_TX_FAULTIndicates SFP laser faultHIGH indicates fault
SOC read (18)SFPA_M-DEF0SFP modul absentHIGH when module physically absent
SOC read (17)SFPA_LOSSFP signal lossHIGH indicates signal loss
SOC read (16)SDCDSD card detectLow when card inserted
SOC read (15)FMC_PRSNT_M2C_LIndicate if FMC installedLow when FMC present
SOC read (14)PG_FMC_VADJIndicate FMC VADJ power is up
SOC read (13)OC_VSATAIndicate SATA pin 7 overcurrent
SOC read (12)USB_OCIndicate USB overcurrent
Signals handeld by RGPIO


VHDL Port nameDirectionSC CPLD PinConnected toFunctionNotes
A_01_NOUTL12JB1, pin 35TX data
A_02_NINJ12JB1, pin 41RX CLK
A_02_PINK12JB1, pin 39RX data
Connection RGPIO to SoM

USR LED

User LEDs are accesible via RGPIO:

Signal VHDLnameFunctionNotes
SoC write(19)LED1-user defined
SoC write(18)LED2-user defined
Connection of User LEDs

LED1 <= rgpio_out_data_i(19) when soc_rgpio_active='1' else Not(PCIE_PERST);

LED2 <= rgpio_out_data_i(18) when soc_rgpio_active='1' else '0';

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.

Revision Changes

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

REV03REV02Clearified PCIe PERST#

v.14

REV03REV02

Martin Rohrmüller

initial version

All


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