Table of Contents
The Cyclone 10 LP Reference Kit is the world's first development board with a 55 kLE (Logic Elements) Intel Cyclone 10 LP and a variety of interfaces for numerous applications. The board is comprehensively tested and ready for use with end products and can also be ordered in customer-specific variants according to your requirements.
Refer to http://trenz.org/tei0009-info for the current online version of this manual and other available documentation.
- Intel Cyclone 10 LP [10CL055YU484C8G]
- Package: UBGA-484
- Speed Grade: 8 (Slowest)
- Temperature: 0 °C to 85° C
- Package compatible device 10CL016, 10CL040, 10CL055, 10CL080 as assembly variant on request is possible
- 16 MBit (2 MByte) Flash Memory (optional up to 32 MBit (4 MByte))
- Integrated USB-JTAG Programmer
- Pin Header Connectors
- 64 MBit (8 MByte) SDRAM (optional up to 512 MBit (64 MByte))
- 64 MBit (8 MByte) User Quad-SPI Flash Memory (optional up to 128 MBit (16 MByte))
- 64 MBit (8 MByte) HyperRAM (Pseudo SRAM) (optional up to 128 MBit (16 MByte))
- 2x MAC Address EEPROM
- 2x Fast Ethernet PHY (10/100 Mbps)
- 8-Channel, 12-Bit, configurable ADC/DAC
- D-Sub Connector
- 2x RJ45 Connector
- Status LEDs, Power LED
- 13x User LEDs
- 7-Segment Display
- Push Buttons:
- 2x Reset Push Buttons
- 5x User Push Buttons
- I/O: 70 GPIO
- 5 V Power Supply
- Dimension: 95 mm x 110 mm
- Reverse Supply Protection
- Undervoltage/Overvoltage Protection
- Power Jack, J12
- RJ45 Socket, J8...9
- D-Sub Connector, J11
- Push Button (Reset), S7
- Grove Connector, J5
- Undervoltage/Overvoltage Protector, U9
- 7-Segment LED, D11
- 1x6 Pin Header, J4
- 1x8 Pin Header, J2...3
- 8x User LEDs (Red), D2...9
- 5x User LEDs (Red), D13...17
- 5x User Push Buttons, S1 - S3...6
- Red LED (CONF_DONE), D10
- PSRAM Memory, U3
- SDRAM Memory, U10
- Voltage Regulator, U4 - U7
- AD/DA Converter, U2
- 6x Pmod Host Socket, P1...6
- Intel Cyclone 10 LP, U1
- Serial Configuration Memory, U5
- 1x10 Pin Header, J1
- EEPROM, U15 - U18 - U20
- FTDI USB 2 to JTAG/UART Converter, U14
- Micro USB 2.0, J10
- Push Button (RST_GPIO), S2
- Oscillator, U22
- Ethernet PHY, U17 - U19
- QSPI Flash Memory, U12
Initial Delivery State
Storage device name
QSPI Flash (U12)
|EEPROM (U18, U20)||Not programmed||Except Ethernet MAC|
|SDRAM (U10)||Not programmed|
|PSRAM (U3)||Not programmed|
|Serial Configuration Memory (U5)||Programmed|
Configuration mode has been set to AS (Active Serial) configuration.
MODE Signal State
|MSEL0||MSEL1||MSEL2||MSEL3||Connected to||Boot Mode|
AS (Active Serial)
|S7, Push Button||Connected to nCONFIG.|
Signals, Interfaces and Pins
I/Os on Pin Headers and Connectors
FPGA bank number and number of I/O signals connected to the connectors:
|FPGA Bank||Connector||I/O Signal Count||Voltage Level||Notes|
|Bank 1||J1 (Pin header)||8 Single ended||3.3 V|
|J2 (Pin header)||8 Single ended||3.3 V|
|J4 (Pin header)||6 Single ended||3.3 V|
J3 (Pin header)
|1 Single ended||3.3 V|
|P1 (Pmod Host Socket)||8 Single ended||3.3 V|
|P2 (Pmod Host Socket)||8 Single ended||3.3 V|
|J11 (VGA Host Socket)||14 Single ended||3.3 V|
|Bank 6||J5 (Grove Connector)||2 Single ended||3.3 V|
|Bank 7||P5 (Pmod Host Socket)||8 Single ended||3.3 V|
|P6 (Pmod Host Socket)||8 Single ended||3.3 V|
|Bank 8||P3 (Pmod Host Socket)||8 Single ended||3.3 V|
|P4 (Pmod Host Socket)||8 Single ended||3.3 V|
Pmod Host Socket
TEI0009 has 6 Pmod 2x6 host sockets which are connected to Cyclon 10 LP (U1).
TEI0009 has 5 pin headers. The pin headers J1...4 are usable for Arduino modules, too.
|Pin Header J1||Signals||Connected to||Notes|
|J1 - 1...6||D8...13||Bank 1|
|J1 - 7||GND|
|J1 - 8||AREF||ADC/DAC|
|J1 - 9||D14_SDA||Bank 1|
|J1 - 10||D14_SCL||Bank 1|
|Pin Header J2||Signals||Connected to||Notes|
|J2 - 1||D0_RXD||Bank 1|
|J2 - 2||D1_TXD||Bank 1|
|J2 - 3...8||D2...4||Bank 1|
|Pin Header J3||Signals||Connected to||Notes|
|J2 - 1||NC||-|
|J3 - 2||3.3V||3.3 V|
|J3 - 3||EXT_RST||Bank 2||Pulled-up to 3.3 V|
|J3 - 4||3.3V||3.3 V|
|J3 - 5||5V||5 V|
|J3 - 6...7||GND||GND|
|J2 - 8||NC||-|
|Pin Header J4||Signals||Connected to||Notes|
|J4 - 1...6||AIN0...5||FPGA Bank 1 and ADC/DAC|
|Pin Header J5||Signals||Connected to||Notes|
|J5 - 1||I2C_SCL||FPGA Bank 6 and EEPROM (U18, U20)||Pulled-up to 3.3V.|
|J5 - 2||I2C_SDA||FPGA Bank 6 and EEPROM (U18, U20)||Pulled-up to 3.3V.|
|J5 - 3||3.3V||3.3 V|
|J5 - 4||GND||GND|
Micro USB 2.0 Connector
FTDI FT2232 (U14) can be accessed through micro USB 2.0 B connector (J10) for JTAG (channel A). Channel B is connected to the FPGA and can be used for UART or other standards.
TEI0009 is equipped with two RJ45 connectors and two Ethernet PHYs. RJ45 connectors J8 and J9 are connected to Ethernet PHYs U17 and U19 respectively.
|Pin||Schematic||ETH1 Pin||ETH2 Pin||Notes|
|TD+||ETH1_TX_P, ETH2_TX_P||U17 - TXP||U19 - TXP|
|TD-||ETH1_TX_N, ETH2_TX_N||U17 - TXM||U19 - TXM|
|RD+||ETH1_RX_P, ETH2_RX_P||U17 - RXP||U19 - RXP|
|RD-||ETH1_RX_N, ETH2_RX_N||U17 - RXM||U19 - RXM|
|LED Green||ETH1_LED0, ETH2_LED0||U17 - LED0/NWAYEN||U19 - LED0/NWAYEN|
|LED Yellow||ETH1_LED1, ETH2_LED1||U17 - LED1/SPEED||U19 - LED1/SPEED|
TEI0009 is equipped with a D-Sub connector which provides interface to Cyclone 10 LP through Bank 2.
|Schematic||Corresponding Signals||Connected to||Notes|
|VGA_RED||VGA_R0...3||Bank 2||Red Channel|
|VGA_GREEN||VGA_G0...3||Bank 2||Green Channel|
|VGA_BLUE||VGA_B0...3||Bank 2||Blue Channel|
|VGA_RGB_HSYNC||VGA_HS||Bank 2||Horizontal Sync|
|VGA_RGB_VSYNC||VGA_VS||Bank 2||Vertical Sync|
QSPI Flash Memory
There is a 64 MBit (8 MByte) QSPI Flash memory (U12) provided by Integrated Silicon Solution Inc. which can be used to store data or configuration. Up to 128 MBit (16 MByte) memory is available on other assembly option.
The TEI0009 has 64 MBit (8 MByte) volatile memory provided by Integrated Silicon Solution Inc., SDRAM IC(U10) for storing user application code and data. Up to 512 MBit (64 MByte) SDRAM is available on other assembly option.
Part number: IS42S16400J-7BL
Supply voltage: 3.3 V
- Clock Frequency: 143 MHz (optional up to 200 MHz)
Temperature: 0°C to 70°C (optional other ranges are available)
The TEI0009 is integrated with 64 Mbit (8 MByte) Pseudo Static Random Access Memory (PSRAM) using a self-refresh DRAM array organized as 8M words by 8 bits. The device supports a HyperBus interface, Very Low Signal Count (Address, Command and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation. Up to 128 MBit (16 MByte) memory is available on other assembly option.
Part number: IS66WVH8M8
Supply voltage: 3.3 V
- Clock Frequency: 100 MHz
Temperature: -40°C to 85°C (optional other ranges are available)
The TEI0009 has a 4-Digit-7-Segment LED display which is connected to Bank 6.
The FTDI chip U14 converts signals from USB 2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet for more information about the capacity of the FT2232H chip.
Channel A of FTDI FT2232H chip is used in MPPSE mode for JTAG. Channel B is routed to FPGA bank 6 and is usable for other standard interfaces.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U15.
|FTDI Chip Pin||Signal Schematic Name||Connected to||Notes|
|ADBUS0||TCK||Bank 1||JTAG interface|
|OSCI||CK12M||12 MHz Oscillator, U16|
|DM||D_N||Micro USB 2.0, J10|
|DP||D_P||Micro USB 2.0, J10|
Serial Configuration Memory
On-board serial configuration memory (U5) is provided by Intel with 16 MBit (2 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 1 via active serial (AS) x1 interface.
|Configuration Memory Pin||Signal Schematic Name||Connected to||Notes|
|DATA1||AS_DATA0||U1, Bank 1|
|DATA0||AS_ASDO||U1, Bank 1|
|nCS||AS_nCS||U1, Bank 1|
U1, Bank 1
The TEI0009 is equipped with two Ethernet PHY (U17, U19) which are connected to two RJ45 (J8, J9) connectors.
|Ethernet PHY Pin||Signal Schematic Names (ETH1/ETH2)||ETH 1||ETH 2||Note|
|TXD0...3||ETH1_TXD0...3, ETH2_TXD0...3||Bank 5||Bank 5|
|TXC||ETH1_TXC, ETH2_TXC||Bank 5||Bank 5|
|TXEN||ETH1_TXEN, ETH2_TXEN||Bank 5||Bank 5|
|RXD0...3||ETH1_RXD0...3, ETH2_RXD0...3||Bank 5||Bank 5|
|RXC/B-CAST_OFF||ETH1_RXC, ETH2_RXC||Bank 5||Bank 5|
|RXER/ISO||ETH1_RXER, ETH2_RXER||Bank 5||Bank 5|
|INTRP/nNAND_Tree||ETH1_INTRP, ETH2_INTRP||Bank 5|
|XI||ETH1_CLKIN, ETH2_CLKIN||Oscillator, U22||Oscillator, U22|
|MDC||ETH1_MDC, ETH2_MDC||Bank 5||Bank 5|
|MDIO||ETH1_MDIO, ETH2_MDIO||Bank 5||Bank 5|
|COL/CONFIG0||ETH1_COL, ETH2_COL||Bank 5||Bank 5|
|CRS/CONFIG1||ETH1_CRS, ETH2_CRS||Bank 5||Bank 5|
|RXDV/CONFIG2||ETH1_RXDV, ETH2_RXDV||Bank 5||Bank 5|
RJ45 - Green LED, J8
RJ45 - Green LED, J9
RJ45 - Yellow LED, J8
RJ45 - Yellow LED, J9
|nRST||ETH1_RST, ETH2_RST||Bank 5||Bank 5|
|RXM||ETH1_RX_N, ETH2_RX_N||RJ45, J8||RJ45, J9|
|RXP||ETH1_RX_P, ETH2_RX_P||RJ45, J8||RJ45, J9|
|TXM||ETH1_TX_N, ETH2_TX_N||RJ45, J8||RJ45, J9|
|TXP||ETH1_TX_P, ETH2_TX_P||RJ45, J8||RJ45, J9|
TEI0009 has three EEPROM, U15, U18 and U20. U15 is pre-programmed for the FTDI FT2232H configuration. U18 and U19 are used for the MAC address configuration.
|Designator||EEPROM Pin||Signal Schematic Names||Connected to||Notes|
|Designator||Pin||Schematic||Connected to||Grove Header||Notes|
|U18, U20||SCL||I2C_SCL||Bank 6||J5|
The TEI0009 module is equipped with a 12-Bit ADC/DAC (U2).
|ADDA_RSTN||Bank 2, U1|
|nSYNC||ADDA_SYNC||Bank 2, U1|
|SCLK||MCLK||Bank 2, U1|
|SDI||MOSI||Bank 2, U1|
|SDO||MISO||Bank 2, U1|
|VREF||AREF||Pin Header, J1||External reference is 1 V to 3.3 V.|
Internal reference is 2.5 V.
Bank 1, U1
Pin Header, J4
|Schematic||Designator||Color||Connected to||Active Level||Note|
|USER_BTN1||S3||Bank 3||User Push Button|
|USER_BTN2||S4||Bank 3||User Push Button|
|USER_BTN3||S5||Bank 3||User Push Button|
|USER_BTN4||S6||Bank 3||User Push Button|
|USER_BTN5||S1||Bank 3||User Push Button|
|U22||Crystal Oscillator||25 MHz|
|U16||Crystal Oscillator||12 MHz|
Power and Power-On Sequence
Power supply with minimum current capability of 3 A for system startup is recommended.
|Intel Cyclone 10 LP FPGA||TBD*|
* TBD - To Be Determined
Power Distribution Dependencies
There is the following power-on sequence. The DCDC converter U7 enables the device U4 according to the diagram below.
Voltage Protection Circuit
There is a transient voltage suppression diode (D12) which protects the board from voltage spikes. Additionaly, there is an overvoltage / undervoltage protection device (U9) for board protection.
VCCIO Schematic Name
|J3||3.3V||2, 4||3.3 V||Out|
Absolute Maximum Ratings
|VIN||Input Supply Voltage (J12)||4.5||5.5||V|
|AREF||External Reference Voltage for ADC/DAC (J1 - 8)||-0.3||3.6||V||Only for input usage.|
|AIN0...5||Input Voltage for ADC/DAC (J4)||-0.3||3.6||V||Only for input usage.|
|AIN6...7||Input Voltage for ADC/DAC (TP1...2)||-0.3||3.6||V||Only for input usage.|
|EXT_RST||External Reset (J3 - 3)||-0.5||4.2||V|
|D0_RXD, D1_TXD, D2...7||Arduino Interface (J2)||-0.5||4.2||V||Only for input usage.|
D8...13, D14_SDA, D15_SCL
|Arduino Interface (J1 - 1...6, 9...10)||-0.5||4.2||V||Only for input usage.|
|I2C_SCL, I2C_SDA||I2C Interface (J5 - 1...2)||-0.3||4.2||V||Only for input usage.|
|Pmod Interface (P1...6)||-0.5||4.2||V||Only for input usage.|
|CLK_IN||External FPGA Clock (J19)||-0.5||4.2||V|
|CLK_OUT||Clock / IO (J20)||-0.5||4.2||V||Only for input usage.|
|T_STG||Storage Temperature||-35||85||°C||See LTC2623WC datasheet|
Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
|D0_RXD, D1_TXD, D2...7||-0.5||3.6||V|
D8...13, D14_SDA, D15_SCL
See SDRAM W9864G6JT datasheet
Module size: 95 mm × 110 mm. Please download the assembly diagram for exact numbers.
- PCB thickness: 1.6 mm.
Currently Offered Variants
Hardware Revision History
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
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