Skip to end of metadata
Go to start of metadata

Table of contents

Overview

Firmware for TEI0022 Intel MAX 10 with designator U41: 10M08SAU169C8G

Feature Summary

  • Fan control
  • JTAG control
  • LED control
  • UART
  • User button
  • Power management
    • Power regulator mode control
    • FMC Power control
  • Reset management
  • Configuration sheme control

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

Name / opt. VHD NameDirectionPinBank PowerDescription
BOOTSEL2outL10+3.3VHPS boot select pin 2
CONF_DONE_IinL5+3.3VCyclone V CONF_DONE pin
CPU_GPIO_0inN10+3.3VVoltage selection via software for FMC_VADJ (U43 → VS0 pin)
CPU_GPIO_1inN9+3.3VVoltage selection via software for FMC_VADJ (U43 → VS1 pin)
CPU_GPIO_2inN11+3.3VVoltage selection via software for FMC_VADJ (U43 → VS2 pin)
CPU_GPIO_3inL1+3.3VFMC power enable control via software
CPU_GPIO_4inH4+3.3VFan control via software
BDBUS0inD1+3.3V_MAX10FTDI UART TXD pin
BDBUS1outC1+3.3V_MAX10FTDI UART RXD pin
EN_0V9outF1+3.3V_MAX10+0.9V power enable
EN_1V8outD12+3.3V_MAX10+1.8V power enable
EN_2V5outA12+3.3V_MAX10+2.5V power enable
EN_3V3outB13+3.3V_MAX10+3.3V power enable
EN_5V0outA7+3.3V_MAX10+5.0V power enable
EN_DDR_FPGAoutE13+3.3V_MAX10FPGA DDR power enable
EN_DDR_HPSoutF13+3.3V_MAX10HPS DDR power enable
EN_FMCoutE1+3.3V_MAX10FMC_VADJ power enable
EN_FMC_3V3outC13+3.3V_MAX10+3.3V FMC power enable
EN_FMC_12VoutC12+3.3V_MAX10+12.0V FMC power enable
EN_VCCoutA10+3.3V_MAX10VCC power enable
FAN_ENoutD13+3.3V_MAX10Fan control
FMC_PG_C2MoutK7+3.3VFMC power good signal to FMC connector
FMC_PRSNT_M2CninJ7+3.3VFMC card detection from FMC connector / currently_not_used
FPGA_GPIO_0outK11VDD_DDR_FPGAFPGA IO (FPGA pin AG10) / FPGA UART RXD
FPGA_GPIO_1inJ10VDD_DDR_FPGAFPGA IO (FPGA pin AH9) / FPGA UART TXD
FPGA_RSTnoutL13VDD_DDR_FPGAFPGA reset
FPGA_RSTn_SWinB4+3.3V_MAX10FPGA reset button
FMC_TCKoutM8+3.3VFMC JTAG TCK
FMC_TDIoutM9+3.3VFMC JTAG TDI
FMC_TDOinM10+3.3VFMC JTAG TDO
FMC_TMSoutM11+3.3VFMC JTAG TMS
FPGA_TCKoutK2+3.3VHPS JTAG TCK
FPGA_TDIoutJ1+3.3VFPGA JTAG TDI
FPGA_TDOinL2+3.3VFPGA JTAG TDO
FPGA_TMSoutJ2+3.3VFPGA JTAG TMS
FTDI_JTAG_TCKinG2+3.3V_MAX10FTDI JTAG TCK
FTDI_JTAG_TDIinF5+3.3V_MAX10

FTDI JTAG TDI

FTDI_JTAG_TDOoutF6+3.3V_MAX10FTDI JTAG TDO
FTDI_JTAG_TMSinG1+3.3V_MAX10FTDI JTAG TMS
HPS_TCKoutK1+3.3VHPS JTAG TCK
HPS_TDIoutM4+3.3VHPS JTAG TDI
HPS_TDOinJ6+3.3VHPS JTAG TDO
HPS_TMSoutM7+3.3VHPS JTAG TMS
HPS_RSTnoutL11+3.3VHPS reset
HPS_RSTn_BOinK6+3.3VBrown Out detection
HPS_RSTn_SWinJ5+3.3VReset button
HPS_WARM_RSTnoutM3+3.3VHPS warm reset
HPS_WARM_RSTn_SWinK5+3.3VHPS warm reset button
JTAGSEL0inF9+3.3V_MAX10Select JTAG connection
JTAGSEL1inE9+3.3V_MAX10Select JTAG connection
LED_1V8outH2+3.3V_MAX10+1.8V power good led
LED_FMC_VADJoutC9+3.3V_MAX10FMC_VADJ power good led
LED_VCCoutF12+3.3V_MAX10VCC power good led
LED_VDD_DDR_FPGAoutE6+3.3V_MAX10FPGA DDR VDD power good led
LED_VDD_DDR_HPSoutH3+3.3V_MAX10HPS DDR VDD power good led
LED_VTT_DDR_FPGAoutD6+3.3V_MAX10FPGA DDR VTT power good led
LED_VTT_DDR_HPSoutG4+3.3V_MAX10HPS DDR VTT power good led
MODEoutA11+3.3V_MAX10+5.0V voltage regulator mode selection
MODE_DDR_FPGAoutE10+3.3V_MAX10Voltage regulator mode selection for FPGA DDR power 
MODE_DDR_HPSoutF10+3.3V_MAX10Voltage regulator mode selection for HPS DDR power
MODE_VCCoutD9+3.3V_MAX10VCC voltage regulator mode selection
MSEL0outN5+3.3VConfiguration mode selection pin 0
MSEL1outN3+3.3VConfiguration mode selection pin 1
MSEL2outN2+3.3VConfiguration mode selection pin 2
MSEL3outN4+3.3VConfiguration mode selection pin 3
MSEL4outN6+3.3VConfiguration mode selection pin 4
nSTATUS_IinL4+3.3VCyclone V nSTATUS pin
PG_1V8inD11+3.3V_MAX10+1.8V power good signal
PG_2V5inC11+3.3V_MAX10+2.5V power good signal
PG_3V3inB12+3.3V_MAX10+3.3V power good signal
PG_5V0inA8+3.3V_MAX10+5.0V power good signal
PG_VCCinB11+3.3V_MAX10VCC power good signal
PG_VDD_FPGAinE12+3.3V_MAX10FPGA VDD DDR power good signal
PG_VDD_HPSinG10+3.3V_MAX10HPS VDD DDR power good signal
PG_VTT_FPGAinB10+3.3V_MAX10FPGA VTT DDR power good signal
PG_VTT_HPSinB5+3.3V_MAX10HPS VTT DDR power good signal
POK_FMCinE3+3.3V_MAX10FMC_VADJ power good signal
PWR_SELoutE4+3.3V_MAX10

Power selection pin for FMC_VCCPD voltage at U37 (Cyclone V - Bank 8A VCCPD voltage)

PWR_SWT_ENoutC10+3.3V_MAX10

Power enable pin for FMC_VCCPD voltage at U37

STATUSoutH1+3.3V_MAX10status led
USER_BTN_FPGAoutG12VDD_DDR_FPGAFPGA user button pin
USER_BTN_HPSoutM2+3.3VHPS user button pin
USER_BTN_SWinB3+3.3V_MAX10user button
VID0_SWinF8+3.3V_MAX10Dip switch S8A for FMC_VADJ voltage selection
VID1_SWinE8+3.3V_MAX10Dip switch S8B for FMC_VADJ voltage selection
VID2_SWinD8+3.3V_MAX10Dip switch S8C for FMC_VADJ voltage selection
VID0outB2+3.3V_MAX10Voltage selection pin 0 (VS0) for FMC_VADJ voltage at U43
VID1outC2+3.3V_MAX10Voltage selection pin 1 (VS1) for FMC_VADJ voltage at U43
VID2outF4+3.3V_MAX10Voltage selection pin 2 (VS2) for FMC_VADJ voltage at U43
JTAGENinE5+3.3V_MAX10enable/disable JTAG access to system controller MAX10
BDBUS2-B1+3.3V_MAX10/ currently_not_used
BDBUS3-A2+3.3V_MAX10/ currently_not_used
BDBUS4-A3+3.3V_MAX10/ currently_not_used
BDBUS5-A4+3.3V_MAX10/ currently_not_used
BDBUS6-A5+3.3V_MAX10/ currently_not_used
BDBUS7-A6+3.3V_MAX10/ currently_not_used
CLK_MAX10-H6+3.3VSI5338A → CLK2A pin / currently_not_used
CLKSEL0-N8+3.3VCyclone V clock select pin 0 / currently_not_used
CLKSEL1-N7+3.3VCyclone V clock select pin 1 / currently_not_used
DEVCLRn-B9+3.3V_MAX10Device-wide reset for MAX 10 / currently_not_used
ETH_RST-G5+3.3VEthernet phy reset / currently_not_used
FMC_SCL-N12+3.3VFMC I²C interface / currently_not_used
FMC_SDA-M13+3.3VFMC I²C interface / currently_not_used
FMC_TRST#-M12+3.3VFMC JTAG test reset / currently_not_used
FPGA_GPIO_2-K12VDD_DDR_FPGAFPGA IO (FPGA pin AF11) / currently_not_used
FPGA_GPIO_3-L12VDD_DDR_FPGAFPGA IO (FPGA pin AG11) / currently_not_used
FPGA_GPIO_4-G13VDD_DDR_FPGAFPGA IO (FPGA pin AA13) / currently_not_used
FPGA_GPIO_5-H13VDD_DDR_FPGAFPGA IO (FPGA pin AB13) / currently_not_used
FPGA_GPIO_6-H8VDD_DDR_FPGAFPGA IO (FPGA pin AK2) / currently_not_used
FPGA_GPIO_7-H9VDD_DDR_FPGAFPGA IO (FPGA pin AK3) / currently_not_used
FPGA_GPIO_8-J9VDD_DDR_FPGAFPGA IO (FPGA pin AJ4) / currently_not_used
FPGA_GPIO_9-K10VDD_DDR_FPGAFPGA IO (FPGA pin AK4) / currently_not_used
FPGA_GPIO_10-J13VDD_DDR_FPGAFPGA IO (FPGA pin AE13) / currently_not_used
FPGA_GPIO_11-J12VDD_DDR_FPGAFPGA IO (FPGA pin AF13) / currently_not_used
FPGA_GPIO_12-H10VDD_DDR_FPGAFPGA IO (FPGA pin AD14) / currently_not_used
HPS_SPI_SS/BOOTSEL0-K8+3.3VHPS boot select pin 0 / currently_not_used
HPS_TRST#-M5+3.3VHPS JTAG test reset / currently_not_used
nCONFIG_I-M1+3.3VCyclone V nCONFIG pin / currently_not_used
QSPI_CS/BOOTSEL1-J8+3.3VHPS boot select pin 1 / currently_not_used
USB_HUB_RST-L3+3.3VUSB hub (U33) reset / currently_not_used
USB_RST-H5+3.3VUSB phy (U8) reset / currently_not_used

Functional Description

Fan control

Can be enabled/disabled through the Intel Cyclone V HPS "CPU_GPIO_4" pin.

JTAG control

The FTDI JTAG is connected to the Intel MAX 10, the Intel Cyclone V HPS and Fabric and to the FMC Connector according to the following table.

JTAGSEL0JTAGSEL1JTAGENJTAG selection
XX1 - (ON)Intel MAX 10
0 - (ON)0 - (ON)0 - (OFF)Cyclone V HPS
0 - (ON)1 - (OFF)0 - (OFF)Cyclone V FPGA
1 - (OFF)0 - (ON)0 - (OFF)FMC

LED Control

LedDescription
LED_1V8connected to PG_1V8
LED_FMC_VADJconnected to POK_FMC
LED_VCCconnected to PG_VCC
LED_VDD_DDR_FPGAconnected to PG_VDD_FPGA
LED_VDD_DDR_HPSconnected to PG_VDD_HPS
LED_VTT_DDR_FPGAconnected to PG_VTT_FPGA
LED_VTT_DDR_HPSconnected to PG_VTT_HPS
STATUS

Status LED (D25). Status depends on blink sequence and priority.

  1. LED OFF : no faults
  2. *ooooooo : CONF_DONE_I is low-> Cyclone V SoC not programmed
  3. **oooooo : not used
  4. ***ooooo : nSTATUS_I failed
  5. ****oooo : pressed FPGA_RSTn_SW button
  6. *****ooo : pressed HPS_RSTn_SW / HPS_WARM_RSTn_SW button
  7. ******** : brown out detection (U54) - HPS_RSTn_BO is low
  8. LED ON : not used

UART

UART signal are routed directly from FTDI chip through Intel MAX 10 to Cyclone V FPGA.

FTDI FT2232H-56QDirectionCyclone V FPGA
BDBUS0 (TXD)FPGA_GPIO_0 (RXD, Pin AG10)
BDBUS1 (RXD)FPGA_GPIO_1 (TXD, Pin AH9)

User button

The user button is connected to the USER_BTN_FPGA pin AB21 and USER_BTN_HPS pin A23 on the Cyclone V FPGA.

Power management

The power sequencing is handled inside the system controller according to the next figure, starting with DCDC U46 +5.0V.


Power Sequencing

Voltage regulator mode control

DesignatorSignalStateDescription
U45

MODE_VCC

1

Forced continous mode
U46MODE1Forced continous mode
U56

MODE_DDR_FPGA

1Pulse-skipping mode for VDD
U50MODE_DDR_HPS1Pulse-skipping mode for VDD

For more information about possible modes see datasheet of voltage regulators.

FMC power control

The FMC adjustable voltage selection FMC_VADJ (U43) can be done by the dip switches VID0_SW (S8A), VID1_SW (S8B) and VID2_SW (S8C) or by the Intel Cyclone V HPS via CPU_GPIO_0 pin, CPU_GPIO_1 pin and CPU_GPIO_2 pin. The choice is done according to the next table.

VID2_SW (S8C)/

CPU_GPIO_2

VID1_SW (S8B)/

CPU_GPIO_1

VID0_SW (S8A)/

CPU_GPIO_0

VoltageNotes
ON / 0ON / 0ON / 03.3V-
ON / 0ON / 0OFF / 12.5V-
ON / 0OFF / 1ON / 01.8V-
ON / 0OFF / 1OFF / 11.5V-
OFF / 1ON / 0ON / 01.25V-
OFF / 1ON / 0OFF / 11.2V-
OFF / 1OFF / 1ON / 00.8Vnot supported by Intel Cyclone V
OFFOFFOFFCPU-dependentselect voltages with CPU_GPIO_0/CPU_GPIO_1/CPU_GPIO_2  pins

The FMC power can be enabled or disabled via software with CPU_GPIO_3 pin, when the dip switches VID0_SW (S8A), VID1_SW (S8B) and VID2_SW (S8C) are set to OFF. If the FMC_VADJ voltage is selected by the dip switches, FMC power is always enabled.

The FMC power sequencing is handled as shown in the next figure.


FMC Power Sequence

Reset Management

The reset buttons are connected via the system controller to the according reset locations.

DesignatorNameconnected toNotes
S1HPS_RSTn_SWHPS_RSTnButton
U54HPS_RSTn_BOHPS_RSTnBrown out detection
S3HPS_WARM_RSTn_SWHPS_WARM_RSTnButton
S4FPGA_RSTn_SWFPGA_RSTnButton

Configuration sheme control

MSEL4MSEL3MSEL2MSEL1MSEL0Configuration sheme
00010FPP x16 Fast, compression feature enabled

Appx. A: Change History and Legal Notices

Revision Changes

SC REV03 to REV04

  • PCB REV03 support only
  • bugfixes
  • add status led control
  • add USER_BTN_HPS, CONF_DONE_I, nSTATUS_I pins

SC REV02 to REV03

  • bugfixes
  • add configuration sheme

SC REV01 to REV02

  • Changed pin connections
  • Changed JTAG connection
  • Changed reset connection
  • Changed FMC Vadj Voltage selection
  • Changed power sequencing

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

REV04REV03Revision 04 release
2020-06-03v.9REV03REV02Thomas DückRevision 03 release
2020-02-19v.7REV02REV02Initial release

All


Legal Notices

Data Privacy

Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy

Document Warranty

The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.

Limitation of Liability

In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.

Copyright Notice

No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.

Technology Licenses

The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

REACH, RoHS and WEEE

REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.




  • No labels