Table of Contents
The Trenz Electronic TEI0023 is a commercial-grade, low cost and small size module integrated with Intel® MAX 10. Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.
Refer to http://trenz.org/tei0023-info for the current online version of this manual and other available documentation.
Intel® MAX 10 FPGA [10M08SAU169C8G]
Speed Grade: C8 (Slowest)
Temperature: 0°C to 85°C (Commercial)
Package compatible device 10M08..10M16 as assembly variant on request possible
SDRAM Memory up to 32 Mbyte (8Mbyte default)
USB 2.0 Multipurpose UART/FIFO IC (FT2232H)
- 4 Kbit EEPROM Memory for FTDI configuration data
- Micro USB Receptacle (communication and power)
- SPI Flash - NOT INSTALLED (only special option)
- 8x User LED's
- 18 Bit 2 MSPS Analog to Digital Converter
2x SMA Female Connector
I/O interface: 23x GPIO - Arduino MKR compatible
Power Supply: 5V
Dimension: 86.5mm x 25mm
- Fully-Differential Programmable-Gain Instrumentation Amplifier
SMA Connector, J5...6
Voltage Reference, U8
Analog to Digital Converter, U6
Voltage Regulator, U4 - U10 - U13 - U16
Switching Voltage Regulator, U11
SDRAM Memory, U2
- Intel® MAX 10 FPGA, U1
SPI Flash Memory, U5 (not populated)
Oscillator, U7 - U19
FTDI USB to JTAG/FIFO Adapter, U3
User LEDs, D2...9
FTDI Configuration EEPROM, U9
Configuration/Status LED (Red) , D10
Power-On LED (Green), D1
Push Button, S1...2
Micro USB Connector, J9
1x14 Pin Header, J2 (Not assembled)
1x6 Pin Header, J4 (Not assembled)
1x4 Pin Header, J3 (Not assembled)
1x14 Pin Header, J1 (Not assembled)
Initial Delivery State
Storage device name
Quad SPI Flash
The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface (using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up. To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile (using a *.SOF file), means the configuration is lost after power off.
FPGA Reconfigration can be triggered by pressing push button S1.
|J2||Connected to nCONFIG|
Signals, Interfaces and Pins
I/Os on Pin Headers and Connectors
|FPGA Bank||Connector Designator||I/O Signal Count||Voltage Level||Notes|
|Bank 1B||J4||5||3.3V||JTAG interface|
FPGA I/O Banks
|FPGA Bank||I/O Signal Count||Connected to||Notes|
|Bank 1A||7||1x14 Pin header, J1||AIN0...6|
|Bank 1B||5||1x6 Pin header, J4||JTAG_EN, TDI, TDO, TMS, TCK|
|Bank 2||1||12MHz Oscillator, U7||CLK12M|
|4||1x14 Pin header, J1||D2...5|
|4||A2D, U6||ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV|
|3||Amplifier, U12||AMP_A0, AMP_A1, AMP_A2|
|1||100MHz Oscillator, U19||CLK_EN|
|Bank 3||22||SDRAM, U2||RAM_ADDR_CMD|
1x14 Pin header, J2
|2||1x14 Pin header, J1||DIO0...1|
|Bank 6||16||SDRAM, U2||DQ0...15|
|Bank 8||8||User Red LEDs, D2...9||LED1...8|
|6||SPI Flash, U5||F_CS, F_CKL, F_DI, F_DO, nSTATUS, DEVCLRn|
|1||Red LED, D10||CONF_DONE|
|6||FTDI JTAG/UART Adapter, U3||BDBUS0...5|
|1||Push Button, S2||USER_BTN|
The Micro-USB connector J9 provides an interface to access the FIFO/UART and JTAG functions via FTDI FT2232H chip. The use of this feature requires that FTDI USB drivers are installed on your host PC.
FTDI FT2232H U3, DP pin
FTDI FT2232H U3, DM pin
JTAG access to the TEI0023 FPGA through pin header connector J4. This is normally not needed as there is on-board USB JTAG functionality.
Pin Header Connector
|JTAG_EN||J4-2||Pulled-up to 3.3V|
|Test Point||Signal||Connected to||Notes|
|TP1||+1.8 V||V_Lin, U13 ↔ A2D, U12|
|TP2||VREF_OUT||V_Lin, U8 ↔ A2D, U6|
|TP6||+14V_A||V_Lin, U10 ↔ Amplifier, U12|
|TP7||-14V_A||V_Lin, U10 ↔ Amplifier, U12|
|TP8||+14.5V||V_Switch, U11 / D11 ↔ L6 / V_Lin u10|
|TP9||-14.5V||V_Switch, U11 / L12 ↔ L7 / V_Lin u10|
|TP10||+5V5_A||u16 ↔ V_Lin, U8 / A2D, U12|
TEI0023 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface.
|SDRAM I/O Signals|
Signal Schematic Name
A0 ... A13
|Bank address inputs|
BA0 / BA1
DQ0 ... DQ15
DQM0 ... DQM1
Row Address Strobe
Column Address Strobe
|WE||bank 3||Write Enable|
The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the features of the FT2232H chip. FTDI FT2232H chip channel A is used in MPPSE mode for JTAG. Channel B is configured to be used as in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.
|FTDI Chip U3 Pin||Signal Schematic Name||Connected to||Notes|
|ADBUS0||TCK||FPGA bank 1B, pin G2||JTAG interface|
|ADBUS1||TDI||FPGA bank 1B, pin F5|
|ADBUS2||TDO||FPGA bank 1B, pin F6|
FPGA bank 1B, pin G1
|BDBUS0||BDBUS0||FPGA bank 8, pin A4||User configurable|
|BDBUS1||BDBUS1||FPGA bank 8, pin B4||User configurable|
|BDBUS2||BDBUS2||FPGA bank 8, pin B5||User configurable|
|BDBUS3||BDBUS3||FPGA bank 8, pin A6||User configurable|
|BDBUS4||BDBUS4||FPGA bank 8, pin B6||User configurable|
|BDBUS5||BDBUS5||FPGA bank 8, pin A7||User configurable|
|BDBUS6||BDBUS6||FPGA bank 6, pin C11||User configurable|
|BDBUS7||BDBUS7||FPGA bank 3, pin J7||User configurable|
|BCBUS0||BCBUS0||FPGA bank 5, pin J9||User configurable|
|BCBUS1||BCBUS1||FPGA bank 3, pin K5||User configurable|
|BCBUS2||BCBUS2||FPGA bank 3, pin L4||User configurable|
|BCBUS3||BCBUS3||FPGA bank 3, pin L5||User configurable|
|BCBUS4||BCBUS4||FPGA bank 3, pin N12||User configurable|
Optional SPI flash device maybe assembled in custom variants, normally it is not populated.
|Signal Schematic Name||Connected to||Notes|
|F_CS||FPGA bank 8, pin B3||Chip select|
|F_CLK||FPGA bank 8, pin A3||Clock|
|F_DI||FPGA bank 8, pin A2||Data in / out|
FPGA bank 8, pin C4
|Data in / out, configuration dual-purpose pin of FPGA|
|DEVCLRN||FPGA bank 8, pin B9||Data in / out, configuration dual-purpose pin of FPGA|
|F_DO||FPGA bank 8, pin B2||Data in / out|
The configuration of FTDI FT2232H chip is pre-programmed in the EEPROM U9.
|FTDI U3, Pin EECS|
|EECLK||FTDI U3, Pin EECLK|
|EEDATA||FTDI U3, Pin EEDATA|
The TEI0023-XX-XXA board is equipped with the Analog Devices ADAQ4003BBCZ 18-bit 2MSPS ADC.
|Instrumentation Amplifier U14, VOUT-|
|IN-||Instrumentation Amplifier U14, VOUT+|
|SDI||FPGA, Bank 2, pin M2, ADC_SDI|
|SDO||FPGA, Bank 2, pin M1, ADC_SDO|
|SCK||FPGA, Bank 2, pin N3, ADC_SCK|
|CNV||FPGA, Bank 2, pin N2, ADC_CNV|
|Designator||Color||Connected to||Active Level||Note|
|D2...9||Red||LED1...8||Active High||User LEDs|
|D10||Red||CONF_DONE||Active Low||Configuration DONE LED|
|D1||Green||3.3V||Active High||After power on it will be on.|
|S2||USER_BTN||User push button||Connected to FPGA Bank 8.|
|Clock Source||Schematic Name||Frequency||Note|
|Microchip MEMS Oscillator, U7||CLK12M||12.00 MHz|
Connected to FTDI FT2232 U3, pin 3.
Connected to FPGA Bank 2, pin H6.
Power and Power-On Sequence
Power supply with minimum current capability of 1A for system startup is recommended.
|Intel MAX 10 10M08 FPGA SoC||TBD*|
* TBD - To Be Determined
Actual power consumption depends on the FPGA design and ambient temperature.
Power Distribution Dependencies
There is no specific or special power-on sequence, just one single power source is needed. After power on the green LED (D1) will be on.
|Power Rail Name|
|VIN||J2-13||-||Input||5 V - Pin Header|
|-||J9-1||Input||5 V - USB Connector|
Absolute Maximum Ratings
|CH1-, CH1+||Analog input voltage on amplifier U12 pin 1, 10||-20||20||V||LTC6373 datasheet|
Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
VIN supply voltage (5.0V nominal)
|Analog input voltage on amplifier U12 pin 1 (CH1-), 10 (CH1+)||-10||10||V||LTC6373 datasheet|
Module size: 25 mm × 86.5 mm. Please download the assembly diagram for exact numbers.
PCB thickness: 1.598 mm.
Currently Offered Variants
Hardware Revision History
|2020-02-03||01||Fill in TRM template||REV01|
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy
The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.
Limitation of Liability
In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.
No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.
The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.
To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.
REACH, RoHS and WEEE
Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).
Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.
Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).
Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.