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SDIO Interface

The SDIO interface is connected from the Polarfire SoC to the B2B connector. If this interface is not necessary, these pins can be used for other functionality.

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anchor Table_OBP_SDIO title SDIO interface description
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true FPGA Bank 4 Connected to B2B Notes MSSIO0 - J1 SDIO_CLK JM1 - 27 MSSIO1 - K5 SDIO_CMD JM1 - 25 MSSIO2 - H1 SDIO_DAT0 JM1 - 23 MSSIO3 - J4 SDIO_DAT1 JM1 - 21 MSSIO4 - K4 SDIO_DAT2 JM1 - 19 MSSIO5 - J7 SDIO_DAT3 JM1 - 17

MSSIO

Six MSSIOs are connected from the Polarfire SoC to the B2B connector.

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anchor Table_OBP_MSSIO title MSSIO interface description
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true FPGA Bank 4 Connected to B2B Notes MSSIO6 - K3 MIO0 JM1 - 97 MSSIO7 - H4 MIO1 JM1 - 91 MSSIO8 - J6 MIO2 JM1 - 99 MSSIO9 - H6 MIO3 JM1 - 87 MSSIO10 - J3 MIO4 JM1 - 95 MSSIO13 - J2 MIO5 JM1 - 93

SGMII Interface

The Polarfire Soc provides two SGMII interfaces whereby one interface is connected to the B2B connector.

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anchor Table_OBP_SGMII title SGMII interface description
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true FPGA Bank 5 Connected to B2B Notes U2 - N8 SGMII1_OUT_N JM3 - 1 U2 - M7 SGMII1_OUT_P JM3 - 3 U2 - K7 SGMII1_IN_N JM2 - 2 U2 - K6 SGMII1_IN_P JM2 - 4

MGT Lanes

There are four MGT (Multi Gigabit Transceiver) lanes and two two clocks connected between the B2B connector JM3 and the Polarfire SoC bank 5. Each MGT lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, signal schematic name, and board-to-board pin connection:

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anchor Table_SIP_MGT title MGT Lanes Connection
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Lane Schematic B2B Note 0 XCVR_RX0_P JM3-26 0 XCVR_RX0_N JM3-28 0 XCVR_TX0_N JM3-25 0 XCVR_TX0_P JM3-27 1 XCVR_RX1_P JM3-20 1 XCVR_RX1_N JM3-22 1 XCVR_TX1_P JM3-19 1 XCVR_TX1_N JM3-21 2 XCVR_RX2_P JM3-14 2 XCVR_RX2_N JM3-16 2 XCVR_TX2_P JM3-13 2 XCVR_TX2_N JM3-15 3 XCVR_RX3_P JM3-8 3 XCVR_RX3_N JM3-10 3 XCVR_TX3_P JM3-7 3 XCVR_TX3_N JM3-9 CLK XCVR_CLK0_P JM3-33 CLK XCVR_CLK0_P JM3-31 CLK XCVR_CLK1_P JM3-32 CLK XCVR_CLK1_N JM3-34

Gigabit Ethernet

On-board Gigabit Ethernet PHY (U7) is provided with Marvell Alaska 88E1512 IC (U7). The Ethernet PHY SGMII interface is connected to the Polarfire SoC.

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anchor Table_OBP_ETH title Gigabit Ethernet pin description
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true ETH Pin Connected to B2B Notes MDIP[0] - 28 PHY_MDI0_P JM1 - 4 MDIN[0] - 27 PHY_MDI0_N JM1 - 6 MDIP[1] - 24 PHY_MDI1_P JM1 - 10 MDIN[1] - 23 PHY_MDI1_N JM1 - 12 MDIP[2] - 22 PHY_MDI2_P JM1 - 16 MDIN[2] - 21 PHY_MDI2_N JM1 - 18 MDIP[3] - 18 PHY_MDI3_P JM1 - 22 MDIN[3] - 17 PHY_MDI3_N JM1 - 24

System Controller CPLD I/O Pins

The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.

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hidden true id Comments
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin Connected to B2B Notes MIO12...14 SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK J2 QSPI

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anchor Table_OBP_SC title System Controller CPLD special purpose pin description
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true CPLD Pin Connected to B2B Notes TDO - 1 TDO JM2 - 97 TDI - 32 TDI JM2 - 95 TCK - 30 TCK JM2 - 99 TMS - 29 TMS JM2 - 93 JTAGENB - 26 JTAGSEL JM1 - 89 - 11 SC_EN1 JM1 - 28 - 12 SC_PGOOD JM1 - 30 - 14 SC_nRST JM2 - 18 - 17 NOSEQ JM1 - 7

SPI Pins

SC_nRST JM2 - 18 - 17 NOSEQ JM1 - 7

USB Interface

USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Polarfire SoC. I/O voltage is fixed at 3.3 V. Reference clock input for the USB PHY is supplied by the on-board 52.00 MHz oscillator (U12).

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anchor Table_OBP_SPIUSB title SPI InterfaceGeneral Overview of the USB PHY Signals
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true PHY Pin Connected to B2B Notes DP - 18, OTG-D_P JM3 - 47 USB data line DM - 19 OTG-D_N JM3 - 49 USB data line CPEN - 17 VBUS_EN JM3 - 53 External USB power switch VBUS - 22 VBUS JM3 - 55 ID - 23 ID JM3 - 51
FPGA Pin (U2)	Signal Name	SPI Pin (U3)	Notes
SCK_3 - E6	SPI_SCK	B2	SS_3	SPI_SS	C2	SDO_3	SPI_SDO	D3	SDI_3	SPI_SDI	D2	SPI_EN_3	SPI_EN