Page History
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- FPGA core logic (1.2V)
- DDR SDRAM (2.5V)
- FPGA bank 3 (2.5V)
- VREF (2.5V)
- VCCCIO0 (2.5V) FPGA bank 0 (if R131+R132- assembly)
Slide Switch S2 = PON
Full power operation (PS_EN = 1): when slide switch S2 is in the right position (PON = power rails unconditionally on), signal PS_EN is set to power rail 3.3V. Thus power rails 2.5V and 1.2V are unconditionally enabled.
Figure 39: S2 on position PON (PS_EN ≠ FX2_PS_EN = x; PS_EN = high ).
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